The TX side runs on QPLL, and the RX and RX_OS runs on CPLL by default.
The OUTCLK frequency is the same as the REFCLK.
The main reason of this modification is that the links should come up
without any DPR access, after power up, using the default reference clock
configuration (122.88 MHz).
This way the user do not need to modify the block design, just
set the required rate in system_bd.tcl.
This commit does not contain any functional changes.
Explicitly select MIO 52 and 53 pins to be part of MDIO port.
MIO_52_PIN (MDIO 0 Clock, Output)
MIO_53_PIN (MDIO 0 Data, Input/Output)
After the tool version change, this pins where by default connected
as MIO GPIOs.
Explicitly disable the "Transfer Start Synchronisation Support"
since the sync lines are not connected in this project.
If the sync input line (s_axi_user[0] or fifo_wr_sync) are not connected,
Vivado 2017.4.1 no longer connects them to the defaultValue defined
in the axi_dmac ip (1). Instead he uses the defaulValue field defined
in the interface definition which in case of both interfaces is 0;
Loop back the unused GPIO pins, and add all the SPI interface to system
wrapper instance.
The following system_top modules were changed:
- ad738x_fmc
- ad7616_sdz
- ad77681evb
- ad77681evb
- ad7768evb
- ad9739a_fmc
- ad9434
- adrv9739
- fmcadc5
- ad6676evb
- ad9265
- ad5766
- fmcomms5
- m2k
The constraint where added to remove timing problems on the reset path.
The constraint paths do not match anymore. The resets are used in a synchronous
way so we don't need the timing exceptions anyway.
Projects affected by this change:
- daq3
- adrv9739
- ad6676evb
- fmcadc5
- daq2/kcu105
- fmcadc2
- adrv9371x
- fmcomms11/zc706
- fmcjesdadc1
By default every base design has a SPI interface (hard or soft). In
case of soft IPs (xilinx), the input registers of the interface by default have
the IOB attribute set to TRUE. If the interface are not used, the tool will
generate a critical warning, stating that IOB registers are not connected to
an IO buffer.
The following constraints are disabling the above setup for every base
design, which using a soft SPI IP.
Set the properties to mirror the hardware configuration so
the Vivado tools can provide warnings if there are any conflicts
between configuration pin settings, such as an IOSTANDARD
on a multi-function configuration pin that conflicts with the
configuration voltage.
see:
https://www.xilinx.com/support/documentation/user_guides/ug570-ultrascale-configuration.pdf
The following base constraints were updated:
- kcu105
- kc705
- vc707
- ac701
To reduce compilation time use default stratagies for synthesis and
implementation. If a project will require custom strategies, enable it
just for that particular project.
This modification will affect both Intel and Xilinx projects.
Vivado sometimes generates semi-valid or invalid warnings and critical warnings.
In the past these messages were silenced, by changing its message severity.
These setups were scattered in multiple scripts. This commit is an attempt
to centralize it and make it more maintainable and easier to review it.
The script specifies the OUT_CLK_SEL and SYS_CLK_SEL parameter values as
binary numbers. But the tools will interpret them as decimal number
resulting in the wrong selection for OUT_CLK_SEL. Specify the parameter
values as decimal values to avoid this.
This is not a critical issue since software will overwrite this setting at
system boot-up. But it should be fixed anyway.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The script specifies the OUT_CLK_SEL and SYS_CLK_SEL parameter values as
binary numbers. But the tools will interpret them as decimal number
resulting in the wrong selection for OUT_CLK_SEL. Specify the parameter
values as decimal values to avoid this.
This is not a critical issue since software will overwrite this setting at
system boot-up. But it should be fixed anyway.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Fixes the following warning:
[Synth 8-2611] redeclaration of ansi port rx_sysref is not allowed
This is a leftover of commit 1c23cf4621 ("all: Update verilog files to
verilog-2001").
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Fixes the following warnings:
[Synth 8-2611] redeclaration of ansi port txnrx_0 is not allowed
[Synth 8-2611] redeclaration of ansi port enable_0 is not allowed
[Synth 8-2611] redeclaration of ansi port enable_1 is not allowed
[Synth 8-2611] redeclaration of ansi port txnrx_1 is not allowed
This is a leftover of commit 1c23cf4621 ("all: Update verilog files to
verilog-2001").
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Make sure that the axi_adxcvr instances are configured with the same
transceiver type as the util_adxcvr.
This is necessary for software to be able to detect the transceiver type
and support dynamic reconfiguration.
It is also necessary for correct eye scan support in the axi_adxcvr block.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Make sure that the axi_adxcvr instances are configured with the same
transceiver type as the util_adxcvr.
This is necessary for software to be able to detect the transceiver type
and support dynamic reconfiguration.
It is also necessary for correct eye scan support in the axi_adxcvr block.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Fix the location assignment of the transceiver blocks to get the correct
lane mapping.
Note that the comments indicating the expected lane mapping are correct,
but the actual transceiver location assignments were not.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The external reference clock runs at 122.88 MHz by default. This means that
the QPLL feedback divider needs to be set to 80 so that the VCO is inside
the locking range (9.8 GHz - 16.375 GHz).
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
DAC data underflow from the DMA, was not connected to anything. This
signal should be connected to the util_rfifo, which will forward it to
the device core.
+ Build both the read and write logic around an FSM
+ Consistent naming of registers and wires
+ Add support for burst lenghts higher than one, current burst lenght
is 64
+ Fix all the bugs, and make it work (first bring up with
adrv9371x/a10soc)
If the ADI_HDL_DIR or ADI_PHDL_DIR are set on Windows platforms, an
invalid TCL character (e.g. backslash) may be used as a file separator,
causing issues with the build / library scripts.
Normalize the paths before using them as global TCL variables.
Add support for the AD-FMCDAQ2-EBZ on the Arria10 SoC development board platform.
In its default configuration the Arria10 SoC development board is not fully
compatible with the AD-FMCDAQ2-EBZ and a slight rework is necessary,
changing the position of four 0 Ohm resistors:
R610: DNI -> R0
R611: DNI -> R0
R612: R0 -> DNI
R613: R0 -> DNI
R620: DNI -> R0
R632: DNI -> R0
R621: R0 -> DNI
R633: R0 -> DNI
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Rework the peripheral address to match the updated semantics of
ad_cpu_interconnect, which expects that the addresses are in the range of
0x00010000 - 0x001fffff. This includes updating the base addresses as well
as compressing the used address range to fit into the 2Mb window.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The DDR memory reference clock on the A10SoC development board is
differential. Currently the EMIF core it is configured for single-ended
configuration, which causes it to generate incorrect IOSTANDARD
constraints. Those incorrect constraints get overwritten again in
system_assign.tcl, so things are working, but this generates a warning when
building the design
Configure the EMIF core correctly and remove the manual constraint overwrite since
they are no longer necessary.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
There is no guarantee that the external reset de-assertion is synchronous
to the sys_clk, yet the clock bridge marks the reset de-assertion as
synchronized to the clock. This can cause recovery or removal timing
violations for the registers affected by this reset signal and potentially
bring the system into an invalid state after the reset is de-asserted.
Mark the reset as not synchronized to the clock signal, this will make sure
that Qsys inserts the proper reset synchronizers where required.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Currently the TX lane mapping is implemented by having to connect tx_phy_s_* to
the tx_ip_s_* and the tx_phy_d_* to the tx_ip_d_* signals in the system
qsys file in the desired order.
Re-work things so that instead the lane mapping is provided through the
TX_LANE_MAP parameter. The parameter specifies in which order logical lanes
are mapped onto the physical lanes.
The appropriate connections are than made inside the core according to this
parameter rather than having to manually connect the signals externally.
In order to generate a 1-to-1 mapping the TX_LANE_MAP parameter can be left
empty.
This change slightly reduces the boiler-plate code that is necessary to
setup the transceiver.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
+ Add a HDL parameter for the PPS receiver module :
PPS_RECEIVER_ENABLE. By default the module is disabled.
+ Add the CMOS_OR_LVDS_N and PPS_RECEIVER_ENABLE into the CONFIG
register
+ Define a pps_status read only register, which will be asserted, if the free
running counter reach a certain fixed threshold. (2^28) The register can
be deasserted by an incomming PPS only.
Some of the standard Quartus components (especially the Merlin cores) generate
quite a few synthesis warnings. Lets assume these are false positives and
disable the warnings.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Istvan Csomortani
AndreiGrozav
Rejeesh Kutty
Adrian Costina
Laszlo Nagy
Lars-Peter Clausen
Michael Hennerich
Matt Fornero
STEVE KRAVATSKY