0360e8587e
Connect JESD204 interrupts
...
Connect the ADI JESD204 link layer peripheral interrupt signals in all
projects.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-05 14:37:50 +02:00
b7ca17f02b
scripts: Change adi_project_create to adi_project_xilinx for creating xilinx projects
2017-06-07 12:06:50 +03:00
50cdb6db67
Merge branch 'jesd204' into dev
2017-05-31 20:44:32 +03:00
84b2ad51e2
license: Add some clarification to the header license
2017-05-31 18:18:56 +03:00
85ebd3ca01
license: Update license terms in hdl source files
...
Fix a few gramatical error, fix the path of the top level license
files.
2017-05-29 09:55:41 +03:00
9a917ae8bf
fmcadc4: Convert to ADI JESD204
...
Convert the FMCADC4 project to the ADI JESD204 link layer core. The change
is very straight forward, but a matching change on the software side is
required.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-23 11:16:07 +02:00
9055774795
all: Update license for all hdl source files
...
All the hdl (verilog and vhdl) source files were updated. If a file did not
have any license, it was added into it. Files, which were generated by
a tool (like Matlab) or were took over from other source (like opencores.org),
were unchanged.
New license looks as follows:
Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
Each core or library found in this collection may have its own licensing terms.
The user should keep this in in mind while exploring these cores.
Redistribution and use in source and binary forms,
with or without modification of this file, are permitted under the terms of either
(at the option of the user):
1. The GNU General Public License version 2 as published by the
Free Software Foundation, which can be found in the top level directory, or at:
https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
OR
2. An ADI specific BSD license as noted in the top level directory, or on-line at:
https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
2017-05-17 11:52:08 +03:00
1c23cf4621
all: Update verilog files to verilog-2001
2017-04-13 11:59:55 +03:00
bc9483c5a2
Ip automatic version: Update ad*/common/ad*_bd.tcl
...
ad6676evb/common/ad6676evb_bd.tcl
ad7616_sdz/common/ad7616_bd.tcl
ad7768evb/common/ad7768evb_bd.tcl
ad9265_fmc/common/ad9265_bd.tcl
ad9434_fmc/common/ad9434_bd.tcl
ad9467_fmc/common/ad9467_bd.tcl
ad9739a_fmc/common/ad9739a_fmc_bd.tcl
adrv9371x/common/adrv9371x_bd.tcl
adv7511/common/adv7511_bd.tcl
fmcadc4/common/fmcadc4_bd.tcl
2017-04-10 18:52:37 +03:00
8063ba2b66
make updates
2017-03-20 16:05:18 -04:00
fb4a583613
projects/system_bd- adc/dac fifo board designs
2017-02-27 16:06:39 -05:00
edd5e9570f
file renamed; sed output; fingers crossed
2017-02-22 15:56:37 -05:00
170c781d02
hdlmake.pl- updates
2016-12-01 13:52:11 -05:00
8f562fd069
xcvr updates- board procedure
2016-11-22 14:43:36 -05:00
4ed7469286
fmcadc4/zc706- updates
2016-11-22 10:32:05 -05:00
0897716167
fmcadc4: xcvr updates
2016-11-15 16:03:52 +02:00
16ee1336c3
Makefile: Update make files
2016-09-15 11:41:06 +03:00
9a2d2e8a02
version_upgrade: Update FMCADC4 to 2016.2
2016-09-13 15:04:11 +03:00
0cd608a7e2
lib_refactoring: Update Make files
2016-08-08 16:38:38 +03:00
df36902713
lib_refactoring: Fix path of the IO macros
2016-08-08 15:07:19 +03:00
d60bce654c
Makefiles: Updated Makefiles so they run correctly with gnuwin32 tools
2016-08-05 15:16:04 +03:00
e42b4ea378
hdlmake- updates
2016-08-04 13:28:25 -04:00
7ca8e10004
make: Update Make files
2016-08-01 14:24:48 +03:00
b0538a03a2
Make: Update
2016-05-06 16:44:24 +03:00
4863a04132
axi_adc/dacfifo: Split the intergration script file
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Split the integration script file into two separate script files. Rename the
integration processes names to be more meaningful.
2016-05-05 09:53:55 +03:00
be74db656c
ad6674evb, fmcadc2, fmcadc4, fmcadc5, fmcjesdadc1:
...
Update system_project.tcl scripts to correctly select the necessary
constraint files
2016-05-04 19:37:33 +03:00
9104b2cc60
ad6676evb, fmcadc2, fmcadc4, fmcadc5,...
...
ad6676evb, fmcadc2, fmcadc4, fmcadc5, fmcjesdadc1: Remove unused
set_proprieties
2016-05-04 19:13:25 +03:00
385ed31a45
make files update
2016-04-29 10:17:35 -04:00
679d471d75
Merge branch 'hdl_2016_r1' into dev
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hdl_2016_r1 contains IP core upgrades to Vivado 2015.4.2 and hdmi_tx improvements.
2016-04-19 18:05:50 +03:00
3006c5a223
make updates
2016-04-11 16:14:59 -04:00
21208ca208
Makefiles: Update Makefiles
2016-03-31 12:37:47 +03:00
334fce03a3
fmcadc4/zc706: Updated design to 2015.4
2016-03-15 15:28:11 +02:00
e8dd5f9788
fmcadc4: Updated common design to 2015.4
2016-03-15 15:27:25 +02:00
977d9d0624
Merge branch 'hdl_2015_r2' into dev
...
Conflicts:
projects/daq1/common/daq1_spi.v
2016-03-02 13:52:15 +02:00
40fb68dfd5
ad9265, ad9434, ad9467, daq1, daq2, daq3, fmcadc2, fmcadc4, fmcadc5, fmcjesdadc1, fmcomms6, fmcomms7, usdrx1: updated common spi module so that spi streaming is possible
2016-03-02 13:39:37 +02:00
ea045a3f9a
fmcadc4: change qpll to receive
2015-12-17 12:34:47 -05:00
5cc97c78d3
Makefiles: Update makefiles to include the nerw axi_gpreg / util_mfifo libraries
2015-11-10 09:32:50 +02:00
ac4091e19e
fmcadc4- add monitor fifo
2015-10-27 14:52:02 -04:00
748a2bc87a
fmcadc4- add ila for zc706 only
2015-10-23 14:32:35 -04:00
b2d0f5c56e
fmcadc4- use the same source/name for clocks
2015-10-23 14:32:35 -04:00
9d2b8809df
Makefiles: Updated Makefiles
2015-10-23 10:44:27 +03:00
07e2d281c0
Make: Update Make files
2015-09-25 19:11:21 +03:00
1604e88242
fmcadc4: Update project to the new JESD interface framework
2015-09-25 19:11:19 +03:00
f4b432da08
fmcadc4: Update to 2015.2
2015-09-25 19:11:17 +03:00
7f5a22a75f
fmcadc4: Drop explicit axi_dmac clock synchronicity configuration
...
The axi_dmac core is now capable of detecting whether its different parts
run in different clock domains or not. No need to configure it manually any
more.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:28:01 +02:00
d52308f074
axi_dmac: Change parameter name 2D_TRANSFER
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Parameter name can't start with numbers, 2D_TRANSFER was changed to DMA_2D_TRANSFER
2015-08-20 10:14:22 +03:00
57cfb7cfb1
hdl/library: Update the IP parameters
...
The following IP parameters were renamed:
PCORE_ID --> ID
PCORE_DEVTYPE --> DEVICE_TYPE
PCORE_IODELAY_GROUP --> IO_DELAY_GROUP
CH_DW --> CHANNEL_DATA_WIDTH
CH_CNT --> NUM_OF_CHANNELS
PCORE_BUFTYPE --> DEVICE_TYPE
PCORE_ADC_DP_DISABLE --> ADC_DATAPATH_DISABLE
CHID --> CHANNEL_ID
PCORE_DEVICE_TYPE --> DEVICE_TYPE
PCORE_MMCM_BUFIO_N --> MMCM_BUFIO_N
PCORE_SERDES_DDR_N --> SERDES_DDR_N
PCORE_DAC_DP_DISABLE --> DAC_DATAPATH_DISABLE
DP_DISABLE --> DATAPATH_DISABLE
PCORE_DAC_IODELAY_ENABLE --> DAC_IODELAY_ENABLE
C_BIG_ENDIAN --> BIG_ENDIAN
C_M_DATA_WIDTH --> MASTER_DATA_WIDTH
C_S_DATA_WIDTH --> SLAVE_DATA_WIDTH
NUM_CHANNELS --> NUM_OF_CHANNELS
CHANNELS --> NUM_OF_CHANNELS
PCORE_4L_2L_N -->QUAD_OR_DUAL_N
C_ADDRESS_WIDTH --> ADDRESS_WIDTH
C_DATA_WIDTH --> DATA_WIDTH
C_CLKS_ASYNC --> CLKS_ASYNC
PCORE_QUAD_DUAL_N --> QUAD_DUAL_N
NUM_CS --> NUM_OF_CS
PCORE_DAC_CHANNEL_ID --> DAC_CHANNEL_ID
PCORE_ADC_CHANNEL_ID --> ADC_CHANNEL_ID
PCORE_CLK0_DIV --> CLK0_DIV
PCORE_CLK1_DIV --> CLK1_DIV
PCORE_CLKIN_PERIOD --> CLKIN_PERIOD
PCORE_VCO_DIV --> VCO_DIV
PCORE_Cr_Cb_N --> CR_CB_N
PCORE_VCO_MUL --> VCO_MUL
PCORE_EMBEDDED_SYNC --> EMBEDDED_SYNC
PCORE_AXI_ID_WIDTH --> AXI_ID_WIDTH
PCORE_ADDR_WIDTH --> ADDRESS_WIDTH
DADATA_WIDTH --> DATA_WIDTH
NUM_OF_NUM_OF_CHANNEL --> NUM_OF_CHANNELS
DEBOUNCER_LEN --> DEBOUNCER_LENGTH
ADDR_WIDTH --> ADDRESS_WIDTH
C_S_AXIS_REGISTERED --> S_AXIS_REGISTERED
Cr_Cb_N --> CR_CB_N
ADDATA_WIDTH --> ADC_DATA_WIDTH
BUFTYPE --> DEVICE_TYPE
NUM_BITS --> NUM_OF_BITS
WIDTH_A --> A_DATA_WIDTH
WIDTH_B --> B_DATA_WIDTH
CH_OCNT --> NUM_OF_CHANNELS_O
M_CNT --> NUM_OF_CHANNELS_M
P_CNT --> NUM_OF_CHANNELS_P
CH_ICNT --> NUM_OF_CHANNELS_I
CH_MCNT --> NUM_OF_CHANNELS_M
4L_2L_N --> QUAD_OR_DUAL_N
SPI_CLK_ASYNC --> ASYNC_SPI_CLK
MMCM_BUFIO_N --> MMCM_OR_BUFIO_N
SERDES_DDR_N --> SERDES_OR_DDR_N
CLK_ASYNC --> ASYNC_CLK
CLKS_ASYNC --> ASYNC_CLK
SERDES --> SERDES_OR_DDR_N
GTH_GTX_N --> GTH_OR_GTX_N
IF_TYPE --> DDR_OR_SDR_N
PARALLEL_WIDTH --> DATA_WIDTH
ADD_SUB --> ADD_OR_SUB_N
A_WIDTH --> A_DATA_WIDTH
CONST_VALUE --> B_DATA_VALUE
IO_BASEADDR --> BASE_ADDRESS
IO_WIDTH --> DATA_WIDTH
QUAD_DUAL_N --> QUAD_OR_DUAL_N
AXI_ADDRLIMIT --> AXI_ADDRESS_LIMIT
ADDRESS_A_DATA_WIDTH --> A_ADDRESS_WIDTH
ADDRESS_B_DATA_WIDTH --> B_ADDRESS_WIDTH
MODE_OF_ENABLE --> CONTROL_TYPE
CONTROL_TYPE --> LEVEL_OR_PULSE_N
IQSEL --> Q_OR_I_N
MMCM --> MMCM_OR_BUFR_N
2015-08-19 14:11:47 +03:00
1de74c0267
fmcadc4: Changed the SPI CS address similar to previous version
2015-07-16 18:22:05 +03:00
c949482574
fmcadc4: Set explicit PCORE_ID for AD9680
2015-07-16 18:21:49 +03:00
a7da779b94
Makefile: Updated Makefiles
2015-07-16 18:19:42 +03:00
Lars-Peter Clausen
Adrian Costina
Istvan Csomortani
AndreiGrozav
Rejeesh Kutty