9 Commits (cf593d5a4046e71738e41c3ed60f09679f78a983)

Author	SHA1	Message	Date
Laszlo Nagy	3183fbf226	adrv9009: update adcfifo/dacfifo	2019-01-23 14:45:45 +02:00
Laszlo Nagy	c9f1c92eaa	adrv9009: use generic TPL ... Make the block design parametrizable. Limitations: F = 1,2,4	2018-12-21 17:32:48 +02:00
Istvan Csomortani	559e00fd75	adrv9009/zcu102: Increase DAC buffer depth to 18Mb	2018-10-11 16:57:30 +03:00
Adrian Costina	e982232d75	adrv9009: Increased DMA clock frequency to ~333 MHz, by enabling AXI SLICES for DMAs	2018-06-12 23:53:56 +03:00
Adrian Costina	801351d93c	adrv9009: Increase sys_dma_clk to 325MHz. At 333 MHz, there are timing violations	2018-06-12 23:53:56 +03:00
Adrian Costina	cc18f76e3b	adrv9009: Reduced DAC FIFO size, as it's not useful for real applications and the memory can be used in other parts of the design	2018-06-12 23:53:56 +03:00
Adrian Costina	65c765eb33	adrv9009: Increase DMA FIFO sizes	2018-06-12 23:53:56 +03:00
Adrian Costina	e445fbe04f	adrv9009: Improved data throughput and DAC FIFO size ... Moved XCVR related connections to HP0, where the HP shares the MUX with the Video DMA HP1 and HP2 are used for RX OS and RX DMAs, sharing the MUX. Usually they shouldn't run at the same time. HP3 is used for TX DMA, sharing the MUX with the FPD DMA controller All HPx and DMA buswidths have been increased to 128 bits The HPx-DMA clock has been increased to 300 MHz DAC FIFO address size has been increased to 17	2018-05-14 11:33:04 +03:00
Adrian Costina	e4d579726d	Renamed ad9379 to adrv9009	2018-04-26 18:19:11 +03:00