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126 Commits (cf5b9b51fd2238f82c33e07ca3ccc6ca1360fd83)

Author SHA1 Message Date
Istvan Csomortani cf5b9b51fd adi_board.tcl : Fix spi ports and hp clocks 2014-04-11 15:31:12 +03:00
Rejeesh Kutty af07f8874f wfifo/rfifo: asynchronous interface 2014-04-10 14:01:40 -04:00
Istvan Csomortani 37e2059fd0 adi_board.tcl : General update 
- Split the adi_dma_interconnect to two procedure:
	  adi_dma_interconnect and adi_hp_assign
	- Fix the adi_spi_core
	- Fix the adi_interconnect_lite
 2014-04-10 18:29:14 +03:00
Rejeesh Kutty 96541f0a7f usdrx1: zc706 updated for usdrx1 2014-04-10 11:05:13 -04:00
Rejeesh Kutty 6f36f74eea usdrx1: common board files 2014-04-10 11:05:11 -04:00
Rejeesh Kutty ac1c145a61 usdrx1: initial checkin 2014-04-10 11:05:10 -04:00
Lars-Peter Clausen dc7b3e085c axi_dmac: Fix issues with non 64-bit AXI masters 
Make sure that the address generator behaves correctly when the buswidth is not
64-bit. Also since the source and destination can have different widths add
separate parameters for source and destination address alignment.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2014-04-10 14:54:22 +02:00
Lars-Peter Clausen 36ef882da0 axi_dmac: data_mover: Improve timing 
We do not know which 'last' condition to use before hand, but we can pre-compute
the result for both conditions and then use them. This removes the comparison
from the already pretty long combinatorial path.

Also simplify a few expressions.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2014-04-10 14:06:44 +02:00
Lars-Peter Clausen 090d3aee04 axi_dmac: Change C_DMA_LENGTH_WIDTH default to 24 
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2014-04-10 13:50:39 +02:00
Lars-Peter Clausen cb630e36a9 axi_dmac: src_fifo_inf: Simplify data path 
Improves timing a bit

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2014-04-10 13:50:39 +02:00
Lars-Peter Clausen f9ca4fb8be axi_fifo: Slightly improve timing 
It is OK to overwrite invalid data with other invalid data.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2014-04-10 13:50:39 +02:00
Lars-Peter Clausen 4c9647f289 axi_dmac: axi_register_slice: Provide default values for registers 
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2014-04-10 13:50:39 +02:00
Lars-Peter Clausen fa5ba6c09d axi_dmac: Make cyclic mode runtime configurable 
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2014-04-10 13:50:39 +02:00
Lars-Peter Clausen 7ca43f4920 axi_dmac: address_generator: Make 'len' registered 
Slightly improves the timing.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2014-04-10 13:50:39 +02:00
Lars-Peter Clausen 66e6c1cc21 axi_dmac: axi_register_slice: Remove reset "latch" from datapath 
Move the datapath updates out of the else branch of the reset condition.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2014-04-10 13:50:39 +02:00
Lars-Peter Clausen 799d2384d8 up_xfer_cntrl: Remove extra semicolon 
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2014-04-10 13:50:39 +02:00
Rejeesh Kutty fbfd658f0d zc706: added pl ddr3 mig 2014-04-09 15:58:12 -04:00
Istvan Csomortani e73952a694 ad9467 : initial checkin 2014-04-09 17:34:40 +03:00
Rejeesh Kutty 8bebc5e3d4 ad9671: initial checkin 2014-04-07 13:01:10 -04:00
Istvan Csomortani 5b0e37b97a adi_project.tcl : Modify implementation strategy 
- Change implementation strategy to Performance Explore.
	  At some projects, this could prevent timing issues, it not
	  increase the overall implementation time in a dramatic way.
 2014-04-07 15:02:38 +03:00
rejeesh kutty 4116247fc0 Update README.md 2014-04-04 16:30:28 -04:00
Rejeesh Kutty 33979fc533 fixes to improve timing - fifo for clock domain transfers 2014-04-04 13:49:53 -04:00
Rejeesh Kutty 6a19b34a00 a5gt: added tightly coupled memory 2014-04-03 20:50:17 -04:00
Rejeesh Kutty 04ab34c8ed a5gt: ethernet assignments 2014-04-03 20:50:16 -04:00
Rejeesh Kutty 12e5cc91bd make signaltap/timing part of the flow 2014-04-03 20:50:15 -04:00
Adrian Costina d0a8b4a63c kc705,common: Mem_interconnect maximize performance 
For FMCOMMS1, when both the ADC and DAC DMAs are active, the system was
unstable. With this fix, it the system seems to be stable.
 2014-04-03 15:59:33 +03:00
Rejeesh Kutty f8f2684b7e up_gt: eyescan delay bug fix 2014-04-02 16:45:41 -04:00
Rejeesh Kutty e85153b5dd altera hal version 2014-04-01 21:12:11 -04:00
Rejeesh Kutty 80e5051894 axi_jesd_gt: initial checkin 2014-04-01 15:14:28 -04:00
Rejeesh Kutty 2472d61daf ad_gt_es: status asserted early for latency 2014-04-01 15:06:51 -04:00
Rejeesh Kutty 04df908fbf altera-fmcjesdadc1 initial checkin 2014-04-01 12:01:57 -04:00
Rejeesh Kutty 0d678b89ed altera a5gt fmcjesdadc1 setup 2014-04-01 11:46:37 -04:00
Rejeesh Kutty 724bd70a06 altera additions and replacements 2014-04-01 11:18:10 -04:00
Istvan Csomortani 8deb36ce08 adi_board.tcl: All procedures works on Zynq/Microblaze 
General patch for the integration procedures. Tested on kc705 and
	zed.
 2014-04-01 16:19:24 +03:00
ATofan 9676146725 FMCOMMS2 AC701 Project 
Not tested - must program Vadj on board
 2014-04-01 15:35:44 +03:00
ATofan e597467447 FMCOMMS2 VC707 Project 2014-04-01 15:34:29 +03:00
ATofan 814b0d72d6 Modified Reset signals for FMCOMMS2 base design 
Made all resets the same (sys_100m_resetn)
 2014-04-01 15:32:48 +03:00
Istvan Csomortani fbafaa8507 MicroBlaze base system: Fix a few net names 
Every interconnect interface net name follows the convention:
	<interconnect name>_<interface name>
	No changes in logic or any connection!
 2014-04-01 10:40:35 +03:00
Adrian Costina f0b8b8f6c0 FMCOMMS1: KC705 updated system_top and constraints 
Needed to be compatible with the latest common file
 2014-03-31 17:49:10 +03:00
Adrian Costina 14b82c03dd FMCOMMS1: Several modifications in the base design 
Corrected the ADC/DAC interrupt location for microblaze systems
Removed the ILA clock generation from sys_audio_clkgen and created a
separate clock generator
All system is reset from the same source
 2014-03-31 17:44:57 +03:00
Adrian Costina a881557645 base_design: Fixed AC701 and VC707 contstraints 
AC701: Modified the IOSTANDARD for some of the pins to correspond to the
AC701 user guide.
VC707: Fixed naming for some system clocks
 2014-03-31 17:38:20 +03:00
Rejeesh Kutty 25f416e46f dds output is reset if disabled 2014-03-31 10:01:49 -04:00
Istvan Csomortani 4ef88a3bed adi_board.tcl : Patch for adi_spi_core process 
- Fix indentation
	- Pacth for adi_spi_core process
 2014-03-31 16:41:07 +03:00
Istvan Csomortani 7f4f200fce Project scripts: Initial check in of adi_board.tcl 
The script contains integration tcl processes.
 2014-03-26 19:08:56 +02:00
Istvan Csomortani f9a67371c0 Zynq Base System: Reset is synchronized to lowest system clock 
System reset (sys_100m_reset) is synchronized to lowest system
	clock (FCLK0), via a Processor System Reset module
 2014-03-26 17:58:14 +02:00
Rejeesh Kutty d3d26e1220 lower the address space requirements 2014-03-26 11:03:45 -04:00
Lars-Peter Clausen 9b4539b7c2 axi_dmac: Add option to configure the FIFO size 
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2014-03-26 12:51:35 +01:00
Adrian Costina ad5ef35b48 fmcomms1: modified *_bd.tcl files formatting 2014-03-26 12:05:42 +02:00
Lars-Peter Clausen ca7a70650d axi_dmac: Delay up_ack by one clock cycle 
The read data also becomes available only with a delay of one clock cycle,
sending the ack too early will result in bogus register reads.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2014-03-25 14:35:52 +01:00
Adrian Costina 8f7d4c9b26 FMCOMMS1: Fixed typo in common/fmcomms1_bd.tcl 2014-03-25 14:34:55 +02:00