Commit Graph

882 Commits (cfe096cdcf9e112b6ae5d6e2ce0b0d207e0e569e)

Author SHA1 Message Date
Lars-Peter Clausen 81a17121b0 axi_dmac: Use internal enable signal for the request generator
All components should use the internal 'do_enable' signal instead of the
external 'enable' signal. The former correctly incorporates the shutdown
sequence and does not get asserted again until the shutdown has been
completed. Using the external signal can cause problems when it is disabled
and enabled again in close proximity.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-02-19 17:04:47 +01:00
Lars-Peter Clausen 23eb0d2428 axi_dmac: request_generator: Stop generating requests when disabled
Currently when the DMAC gets disabled the request_generator will still
generate all remaining burst requests for the currently active transfer.
While these requests will be ignored by the source and destination component
this can still take a fair amount of time for long transfers.

So just stop generating burst requests once the DMAC is being disabled.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-02-19 17:04:47 +01:00
Lars-Peter Clausen e15f0cd2c6 dmac: fifo_inf: Handle overflow and underflow correctly
Refactor the fifo_inf modules to always correctly generate the underflow and
overflow status signals. Before it was possible that in some cases they
were not generated when they should have been.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-02-19 17:04:47 +01:00
Lars-Peter Clausen ea84e93e1d axi_dmac: Correctly handle shutdown for the request splitter
We need to make sure to not prematurely de-assert the s_valid signal for the
request splitter when disabling the DMAC. Otherwise it is possible that
under certain conditions the DMAC is disabled with a partially accepted
request and when it is enabled again it will continue in an inconsistent
state which can lead to transfer corruption or pipeline stalls.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-02-19 17:04:31 +01:00
Lars-Peter Clausen 96b2a6d49a axi_dmac: Use internal enable signal for the request generator
All components should use the internal 'do_enable' signal instead of the
external 'enable' signal. The former correctly incorporates the shutdown
sequence and does not get asserted again until the shutdown has been
completed. Using the external signal can cause problems when it is disabled
and enabled again in close proximity.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-02-19 17:04:31 +01:00
Lars-Peter Clausen 4a69569265 axi_dmac: request_generator: Stop generating requests when disabled
Currently when the DMAC gets disabled the request_generator will still
generate all remaining burst requests for the currently active transfer.
While these requests will be ignored by the source and destination component
this can still take a fair amount of time for long transfers.

So just stop generating burst requests once the DMAC is being disabled.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-02-19 17:04:31 +01:00
Lars-Peter Clausen 6711390c01 dmac: fifo_inf: Handle overflow and underflow correctly
Refactor the fifo_inf modules to always correctly generate the underflow and
overflow status signals. Before it was possible that in some cases they
were not generated when they should have been.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-02-19 17:04:31 +01:00
Rejeesh Kutty 8839c8b18c xfer-logic: stretch toggles to allow capture 2015-02-06 22:07:00 -05:00
Rejeesh Kutty 8050a14bd8 xfer-logic: stretch toggles to allow capture 2015-02-06 22:06:56 -05:00
Istvan Csomortani 890bb1da75 daq2: Add support for VC707 2015-01-29 18:33:27 +02:00
Rejeesh Kutty 8fedb5b41c fifo2s: qualify last with valid 2015-01-15 09:34:43 -05:00
Adrian Costina 623e732ee6 kc705: Updated base project with linear flash. Updated all depending projects 2015-01-13 10:07:51 +02:00
Rejeesh Kutty 117686f352 ad9739a: updates for ad9739a 2015-01-09 10:54:50 -05:00
Rejeesh Kutty 785d3a4ae3 ad9739a: updates for ad9739a 2015-01-09 10:54:40 -05:00
Rejeesh Kutty e8d0782a2e ad9739a: updates for ad9739a 2015-01-09 10:54:22 -05:00
Rejeesh Kutty baea2090d6 ad9739a: updates for ad9739a 2015-01-09 10:54:12 -05:00
Rejeesh Kutty c9b6411e86 ad9739a: updates for ad9739a 2015-01-09 10:54:00 -05:00
Rejeesh Kutty a9cc8f6c91 ad9739a_fmc: added 2015-01-08 10:35:59 -05:00
Rejeesh Kutty 63633a0fa5 ad9739a: constraints 2015-01-08 10:25:45 -05:00
Rejeesh Kutty ed73a9d1cf ad9739a: updated to ad9739a 2015-01-08 10:25:15 -05:00
Rejeesh Kutty ad4b4f64d0 ad9739a: ad9122 copy 2015-01-07 15:36:02 -05:00
Rejeesh Kutty b65bcab8d6 up_clkgen: reading typo 2015-01-07 13:58:43 -05:00
Istvan Csomortani 3db1cf0872 README: Add tools version 2015-01-06 10:24:06 +02:00
Istvan Csomortani 4a9c4cdf19 fmcadc2_zc706: Fix PLDDR fifo name 2014-12-19 13:01:33 +02:00
Istvan Csomortani 6230cb25b7 fmcomms7_zc706: Add constraint file for PLDDR 2014-12-19 13:01:27 +02:00
Istvan Csomortani 6e124c4c24 fmcomms7_zc706: Connect PLDDR rst to external push button 2014-12-19 13:01:21 +02:00
Istvan Csomortani a0b83bac7f fmcomms7_zc706: Delete trailing spaces from system top 2014-12-19 13:01:15 +02:00
Istvan Csomortani 362b0f5300 daq3_zc706: Add constraint file for PLDDR 2014-12-19 13:01:10 +02:00
Istvan Csomortani d77e28e372 daq3_zc706: Connect PLDDR rst to external push button 2014-12-19 13:01:05 +02:00
Istvan Csomortani d483801e2d daq3_zc706: Delete trailing spaces from system_top 2014-12-19 13:00:59 +02:00
Istvan Csomortani df205f5cea fmcadc2_zc706: Connect PLDDR rst to external push button 2014-12-19 13:00:53 +02:00
Istvan Csomortani 8fc1f046a4 fmcadc4_zc706: Add constraint file for PLDDR 2014-12-19 13:00:48 +02:00
Istvan Csomortani 7ec1e282d9 daq2_zc706: Add constraint file for the PLDDR 2014-12-19 13:00:42 +02:00
Istvan Csomortani a6cf615ee0 zc706_constr: Move the sys_rst related constraint definition to zc706_system_mig_constr.xdc 2014-12-19 13:00:35 +02:00
Rejeesh Kutty c3529f112f up_gt: move status to up clock 2014-12-19 13:00:27 +02:00
Rejeesh Kutty 153a4cef18 daq2: missing sys_rst decl. 2014-12-19 13:00:21 +02:00
Rejeesh Kutty f4774d6f98 fifo2s: false path typo on source signals 2014-12-19 13:00:13 +02:00
Rejeesh Kutty ad144ef06a plddr3: sys-rst from board pushbutton 2014-12-19 13:00:07 +02:00
Rejeesh Kutty 33a8c8a155 plddr3: sys-rst from board pushbutton 2014-12-19 13:00:01 +02:00
Rejeesh Kutty 0cc29fe03b plddr3: sys-rst from board pushbutton 2014-12-19 12:59:54 +02:00
Rejeesh Kutty 51bdcb1b12 plddr3: sys-rst from board pushbutton 2014-12-19 12:59:48 +02:00
Rejeesh Kutty daba3fb72e plddr3: sys-rst from board pushbutton 2014-12-19 12:59:42 +02:00
Rejeesh Kutty 758ac6bb8e plddr3: sys-rst from board pushbutton 2014-12-19 12:59:35 +02:00
Adrian Costina 1a9eb8196a VC707: Fixed linear flash timings 2014-12-18 17:49:00 +02:00
Adrian Costina 656246f2ba fmcomms2: Updated VC707 project to fix ethernet problem 2014-12-17 16:16:01 +02:00
Rejeesh Kutty c4249ae274 Merge branch 'hdl_2014_r2' 2014-12-11 11:33:05 -05:00
Istvan Csomortani 9e8fd8ed9e base_design: External IIC reset is connected to Vcc
External IIC reset is connected to Vcc in case of AC701, KC705 and VC707
2014-12-11 11:14:54 +02:00
Rejeesh Kutty 842ba19aaa fmcomms2/ml605: compilation fixes 2014-12-09 14:31:12 -05:00
Rejeesh Kutty d7a6b5e6d0 fmcomms2/ml605: compilation fixes 2014-12-09 14:31:11 -05:00
Rejeesh Kutty d57b6b01c6 fmcomms2/ml605: compilation fixes 2014-12-09 14:31:10 -05:00