d0166a4c7e
ccbox- updates
2016-11-17 10:24:11 -05:00
c2b7cbd61b
ccbox- constraints
2016-11-17 10:23:51 -05:00
5e6b931150
ccbox- added
2016-11-17 09:28:33 -05:00
fb5d36b250
pzsdr2- update ccfmc
2016-11-16 16:27:41 -05:00
95c44b687e
pzsdr2- fmc/pci constraints
2016-11-16 16:27:41 -05:00
11347c49be
fmcomms11- device set to -3
2016-11-16 13:43:07 -05:00
b85a282748
fmcomms11- lane swap
2016-11-16 10:26:47 -05:00
bdd14c3874
README: Delete second rule under headers
...
By default there is a rule under each header, no need for another one.
2016-11-16 11:04:43 +02:00
81e47edcd5
README: Set links for documentation
2016-11-16 10:57:39 +02:00
fabbe4981e
Update README.md
...
updated
2016-11-15 16:15:55 -05:00
538a1c977f
pzsdr2: make files
2016-11-15 16:00:55 -05:00
4905e80df8
Update README.md
...
updated
2016-11-15 14:16:46 -05:00
db243df97e
pzsdr2- updates
2016-11-15 14:16:06 -05:00
0897716167
fmcadc4: xcvr updates
2016-11-15 16:03:52 +02:00
cac4057449
daq2/common: Altera updates
2016-11-15 16:03:52 +02:00
cfd3ea61f1
pzsdr-to-pzsdr2
2016-11-14 14:12:22 -05:00
9d6c93a5d8
Fix warnings
2016-11-14 15:17:15 +02:00
12d6e46ae7
clean: Delete deprecated source files
...
The axi_jesd_gt was repleaced by axi_adxcvr IP, which is located
at library/xilinx and library/altera.
The axi_jesd_xcvr was an early version of axi_adxcvr.
The register map is moved to the IP's directory.
2016-11-14 10:43:46 +02:00
f64b44c8ac
sdrstk2pluto- contents
2016-11-11 13:52:57 -05:00
2ececad58c
sdrstk-2-pluto
2016-11-11 13:49:04 -05:00
c80033cb1b
util_fir_int: removed s_axis_data_tvalid and updated sdrstk
2016-11-11 17:52:19 +02:00
e62fe0c086
fmcjesdadc1- a5gt/a5soc- sysclk is different
2016-11-11 10:34:18 -05:00
6f4dc92dd2
util_fir_int: Fix channel data assignment
2016-11-11 15:46:17 +02:00
7008c641b5
axi_adrv9371/zc706: Constraints update
...
From source *jesd_rstgen* is a false path for TX and RX_OS too.
2016-11-11 10:35:09 +02:00
85eac8c811
fmcjesdadc1/a5*- updates
2016-11-10 16:57:06 -05:00
959055bd54
common/a5gt- updates
2016-11-10 16:56:35 -05:00
7a2c713a4e
fmcjesdadc1/a5* - hdlmake.pl
2016-11-10 11:37:06 -05:00
c6730ab2d7
fmcjesdadc1/a5gt- updates
2016-11-10 11:36:41 -05:00
c207589f4b
fmcjesdadc1/a5gt - qsys2tcl flow
2016-11-10 11:32:29 -05:00
8af0731bb0
a5gt- qsys2tcl flow
2016-11-10 11:30:18 -05:00
7a606cbae1
sdrstk: Maximum clock frequency is 61.44 in CMOS mode
2016-11-10 17:45:35 +02:00
64d1d54ec0
util_fir_int: Update filter, as it's used with ad9361 in CMOS mode
2016-11-10 17:45:03 +02:00
66098b7ae7
util_fir_dec: Update filter, as it's used with ad9361 in CMOS mode
2016-11-10 17:43:04 +02:00
d29ef14f36
sdrstk: Configured ad9361 in 1r1t mode
2016-11-10 17:06:42 +02:00
a54092c9bb
fmcjesdadc1: Update projects to xcvr framework
...
This commit contains modifications for Xilinx only
2016-11-10 10:59:52 +02:00
6073cdded4
axi_ad9250: Tie rx_valid to ground
2016-11-10 10:52:37 +02:00
8845aeb6ab
axi_ad9250: Add missing file to Make and script
2016-11-10 10:48:46 +02:00
d6918de19e
ad6676: Update projects to xcvr frame work
2016-11-10 10:39:46 +02:00
8493bd4329
axi_ad6676: Update the core, sof interface added
2016-11-10 10:39:33 +02:00
3cc416ca60
pzsdr1- fix typo on system_ps7
2016-11-09 12:04:30 -05:00
35c2dd5d6d
adrv9371x/zc706: Fix constraints
2016-11-09 16:34:08 +02:00
0b58a2a1db
avl_adxcvr- sysclk frequency
2016-11-09 09:21:07 -05:00
aef3e87d7e
fmcjesdadc1/a5soc -- xcvr frame work updates
2016-11-08 15:20:48 -05:00
53c2f0642b
fmcjesdadc1/a5soc -- xcvr frame work updates
2016-11-08 15:20:33 -05:00
48ee720901
avl_adxcvr- a5 requires single transceiver controller
2016-11-08 15:20:01 -05:00
f0af8216ce
common/a5soc- device can not run at 100M cpu clock
2016-11-08 15:19:23 -05:00
d9cfccc05f
common/a5soc- gpio in/out separation
2016-11-08 15:19:02 -05:00
a58597c13a
ad9250 - build fixes
2016-11-08 15:17:54 -05:00
d7357d781b
axi_ad9250 - avalon/axi streaming + sof
2016-11-04 15:30:39 -04:00
acb9bf3902
hdlmake- a5soc/a5gt- updates
2016-11-04 15:02:57 -04:00
Rejeesh Kutty
István Csomortáni
AndreiGrozav
Istvan Csomortani
Adrian Costina