AndreiGrozav
679d471d75
Merge branch 'hdl_2016_r1' into dev
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hdl_2016_r1 contains IP core upgrades to Vivado 2015.4.2 and hdmi_tx improvements.
2016-04-19 18:05:50 +03:00
Rejeesh Kutty
bf6ef4e5f3
board- add disconnect
2016-04-11 15:33:00 -04:00
AndreiGrozav
71be9519ec
adi_project.tcl: Updated to 2015.4
2016-03-15 15:03:50 +02:00
Rejeesh Kutty
b147e9c94a
pzsdr1- updates
2016-02-02 12:33:01 -05:00
Rejeesh Kutty
bcac3eef4d
pzsdr1- initial commit
2016-01-25 16:07:33 -05:00
Lars-Peter Clausen
51d20b1a61
adi_project.tcl: Add MicroZed support
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Handle the projects for the MicroZed and set up the FPGA part accordingly.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-01-13 20:32:26 +01:00
Istvan Csomortani
ef9bdf6ec9
adi_project: Regenerate the layout of the IP Integrator subsystem design.
2015-11-09 11:01:10 +02:00
Adrian Costina
afc4274ee3
common scripts: Changed the resulting hdf file to system_top_bad_timing, if design doesn't meet timing.
2015-11-06 16:01:19 +02:00
Adrian Costina
0c7c0f2cd8
common scripts: Change the name of the generated HDF if the design doesn't meet timing
2015-11-05 18:41:51 +02:00
Istvan Csomortani
c83239b014
fmcomms2/zc706pr: Update PR design
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+ Add system_top.v to design
+ Add pr specific constraints
2015-10-09 13:23:42 +03:00
Rejeesh Kutty
48af5f29de
rfsom renamed to pzsdr
2015-09-18 11:19:50 -04:00
Istvan Csomortani
971e3395e7
projects/scripts: Update board part names.
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Property 'board' is deprecated for object type 'project', 'board_part' is used. Update the 'board_part' property names for all Xilinx development boards.
2015-08-25 10:19:57 +03:00
Istvan Csomortani
0dfb3e2019
tcl_scripts: Update Vivado version number to 2015.2.1
2015-08-20 10:50:52 +03:00
Lars-Peter Clausen
6862655b0d
Add .gitattributes file
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Add .gitattributes file which sets up the eol encoding handling. This will
make sure that we get a uniform eol encoding across different operating
systems.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 11:07:10 +02:00
Rejeesh Kutty
db76fe3298
tquest- generate the timing report file
2015-06-19 14:32:53 -04:00
Rejeesh Kutty
886c24f597
tq-alt: added
2015-06-04 10:53:14 -04:00
Lars-Peter Clausen
c53f8c15ee
Add CN0363 project
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Add support for the CN0363 (colorimeter) board connected to the ZED board.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-21 17:21:35 +02:00
Rejeesh Kutty
e489090fbb
scripts- initialize prcfg list
2015-05-04 12:34:19 -04:00
Istvan Csomortani
e7a0da9089
fmcomms2 : Verify the existence of the PR license
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The fmcomms2 runs by default on PR mode, if the project script does not find a PR license, will implement just the default mode.
2015-05-04 15:12:38 +03:00
Rejeesh Kutty
4bb26caa13
itx045: default install
2015-05-01 16:19:10 -04:00
Rejeesh Kutty
26fb85583b
adi_project- prefix directory for gitignore & make clean
2015-05-01 13:18:12 -04:00
Rejeesh Kutty
0dc4c9cda9
adi_project: added partial reconfiguration
2015-05-01 12:21:59 -04:00
Rejeesh Kutty
ee2cd034bc
scripts: add gnd/vcc connections
2015-03-26 10:08:01 -04:00
Istvan Csomortani
f7dd466469
adi_board.tcl : Fix some issue with the ad_mem_hpx_interconnect
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Sometimes the find_bd_objs does not do its job, so need to double check that the interface clock is already connected to the p_clock or not.
Not sure about the cause of this behavior, need more investigation. Issue was found first at KC705 base design.
2015-03-13 18:51:21 +02:00
Rejeesh Kutty
17d8c1b72b
daq2: move intrs into ipi
2015-03-12 16:17:17 -04:00
Rejeesh Kutty
c0eef42647
adi_board: enable ps7 hp if needed
2015-03-09 16:12:23 -04:00
Rejeesh Kutty
ed28b47203
board: optimize interconnect for performance
2015-03-06 12:38:52 -05:00
Rejeesh Kutty
da5b136f5a
daq2+base: board tcl updates
2015-03-05 10:56:36 -05:00
Rejeesh Kutty
0ac1676318
daq2+base: board tcl updates
2015-03-05 10:56:36 -05:00
Rejeesh Kutty
4f918cdce9
2014.4.1 ultrascale updates
2015-02-26 16:10:57 -05:00
Rejeesh Kutty
b9d16a7eb1
scripts: renaming board parameters
2015-02-20 09:12:30 -05:00
Rejeesh Kutty
024d9e7309
replace export hardware -- hwdef/sysdef
2015-01-13 13:40:21 -05:00
Rejeesh Kutty
0258afbadc
board: add ddr seg variable
2015-01-09 14:12:50 -05:00
Rejeesh Kutty
43037a42eb
scripts: 2014.4 update
2014-12-23 14:03:51 -05:00
Lars-Peter Clausen
84052ad437
Add Vivado version check to adi_project_create
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The scripts generating the projects files typically only work correctly with
one specific version of Vivado. If a incorrect version is used the script
may fail at some point with a cryptic error message or may not fail but
create a bitstream that is not working as expected, e.g. unconnected
signals, etc. This patch adds a version check to adi_project_create that
will error out early on stating that the wrong version of Vivado was used
and which is the right version to use.
By default the required version will be the version that is required by the
common scripts. Individual projects can overwrite the required version by
setting the REQUIRED_VIVADO_VERSION variable to the required version or can
bypass the version check completely by setting the IGNORE_VERSION_CHECK
variable to 1.
Callers of the script can also disable the version check by setting the
ADI_IGNORE_VERSION_CHECK environment variable.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-11-26 10:46:34 +01:00
Istvan Csomortani
1834cf6d38
adi_prcfg_project: Update the PR design flow
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Optimization directive kept on default in the implementation flow.
2014-11-21 19:26:33 +02:00
Istvan Csomortani
c0f4d7e2b5
mitx045_common: Definition file patch
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In 2014.2 tool version, the way how a definition file needs to be applied is different
The command "apply_bd_automation" should be used, instead setting property PCW_IMPORT_BOARD_PRESET
In non-project mode (PR design flow), after creating the static design the type of the board is set.
NOTE: the definition file for mitx must be installed accordingly in order to get this work
See link: http://zedboard.org/support/documentation/2056
2014-11-21 19:14:37 +02:00
Istvan Csomortani
bbf1f0c156
adi_project: Add board definition for mitx045
2014-11-18 10:05:57 +02:00
Istvan Csomortani
eaacd4d49a
adi_project.tcl: Fix message severity (working solution)
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Need to define the default/initial severity too.
2014-11-13 18:55:43 +02:00
Istvan Csomortani
4bcf338e9b
adi_project.tcl : Fix message severity
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When message severity is set to 'error', need to do it quiet, other way the tool will stop after synthesis, complaining for previous errors.
2014-11-13 16:33:47 +02:00
Istvan Csomortani
776a396141
adi_project.tcl: Add new message severity definition
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Set "Parameter does not exist!" message severity to error.
2014-11-11 19:20:40 +02:00
Rejeesh Kutty
c1268f089d
scripts: hp/mem updates
2014-11-10 15:06:20 -05:00
Istvan Csomortani
e0b7ef2f4f
scripts: Update scripts for PR design flow
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+ Rewrite the pr_verify process, to improve verification time
+ Update the implementation flow: always the biggest logic will be implemented first, to achieve a better result
therefore force the tool to optimize the first logic with 'ExploreSequentialArea'
+ Make utilization report just from the PR pblock, that's more relevant as the utilization report of the whole fabric
2014-10-30 18:51:13 +02:00
Rejeesh Kutty
fd66affa42
scripts: add default memory interconnect
2014-10-27 15:53:20 -04:00
Rejeesh Kutty
fc4e002150
scripts: add mb cpu side
2014-10-27 15:53:19 -04:00
Rejeesh Kutty
54f341fad8
scripts: sdk export before timing check
2014-10-27 09:59:52 -04:00
Rejeesh Kutty
4494998940
scripts: ignore another variant of reset warning
2014-10-27 09:59:51 -04:00
Rejeesh Kutty
f3c9627cae
adi_project: demote reset warnings to info
2014-10-17 14:38:13 -04:00
Rejeesh Kutty
0aed11fa6c
adi_project: demote useless warnings
2014-10-15 14:50:54 -04:00
Rejeesh Kutty
210da4116f
scripts: initial commit
2014-10-03 16:13:34 -04:00
Istvan Csomortani
f2cd7626f5
adi_project : ZC706 board name changed on 2014.2
2014-09-22 17:33:49 +03:00
Istvan Csomortani
49a77c0413
prcfg: Generate configuration files to *.bin
2014-07-24 09:43:00 +03:00
Rejeesh Kutty
57bb3705f2
zc706-plddr3: read changes to lower dma clock
2014-06-25 09:20:58 -04:00
Istvan Csomortani
3d8d576532
prcfg_script: Update the PR flow script
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+ Make part global
+ No need the Explore directive on implementation
+ Fix some reference to pr module
+ Fix the pr_verify function
2014-06-13 20:33:59 +03:00
Istvan Csomortani
bd8d355b05
scripts: Update adi_prcfg_project.tcl
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Define a new parameter for the prcfg_init_workspace process:
prcfg_name_list.
2014-06-06 15:00:23 +03:00
Istvan Csomortani
f452e40192
scripts: Initial check in of non-project flow
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These processes are used for projects with partial
reconfiguration. The used design flow in these cases is the
non-project (batch) design flow.
2014-06-05 14:33:27 +03:00
Adrian Costina
c52327d0c6
common,adv7511: Added mitx045 platform.
2014-06-02 11:08:03 +03:00
Rejeesh Kutty
51c0ee1e20
ml605: tcl updates
2014-05-06 09:29:21 -04:00
Rejeesh Kutty
ef60cce15e
kcu105: added
2014-04-30 14:41:40 -04:00
Istvan Csomortani
179d6d601c
adi_board.tcl : Use 'global' instead of '$::'
2014-04-14 11:45:35 +03:00
Istvan Csomortani
c718169f27
adi_board.tcl : Fix the address assignment command
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A lot of cores have more than one address segments, therefor need
to filter out the segment of the axi lite interface
2014-04-11 16:14:56 +03:00
Istvan Csomortani
cf5b9b51fd
adi_board.tcl : Fix spi ports and hp clocks
2014-04-11 15:31:12 +03:00
Istvan Csomortani
37e2059fd0
adi_board.tcl : General update
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- Split the adi_dma_interconnect to two procedure:
adi_dma_interconnect and adi_hp_assign
- Fix the adi_spi_core
- Fix the adi_interconnect_lite
2014-04-10 18:29:14 +03:00
Istvan Csomortani
5b0e37b97a
adi_project.tcl : Modify implementation strategy
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- Change implementation strategy to Performance Explore.
At some projects, this could prevent timing issues, it not
increase the overall implementation time in a dramatic way.
2014-04-07 15:02:38 +03:00
Istvan Csomortani
8deb36ce08
adi_board.tcl: All procedures works on Zynq/Microblaze
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General patch for the integration procedures. Tested on kc705 and
zed.
2014-04-01 16:19:24 +03:00
Istvan Csomortani
4ef88a3bed
adi_board.tcl : Patch for adi_spi_core process
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- Fix indentation
- Pacth for adi_spi_core process
2014-03-31 16:41:07 +03:00
Istvan Csomortani
7f4f200fce
Project scripts: Initial check in of adi_board.tcl
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The script contains integration tcl processes.
2014-03-26 19:08:56 +02:00
Adrian Costina
698e9f4757
Added phys_opt_design step for fixing timing
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The FMCOMMS1 meets timing on ZED/ZC702 only if the phys_opt_design step
is part of the implmentation flow, with the Explore argument.
"This step performs physical optimizations such as timing-driven
replicaiton of high fanouts nets to improve timing results"
2014-03-19 16:42:44 +02:00
Istvan Csomortani
7a6ce70e19
Fix default repository path for adi_project.tcl
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Projects can be build by running 'source system_project.tcl' in
Vivado Tcl console.
2014-03-13 10:28:16 +02:00
Rejeesh Kutty
f3ae57a53e
global clock and reset names
2014-03-11 09:57:59 -04:00
Istvan Csomortani
793bf2f350
Change the adi_project_run process to prevent "const_type UCF" issue
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- Set the constraint type to XDC before run the synthesis
2014-03-07 11:06:11 +02:00
Rejeesh Kutty
350ec5e633
changed path settings
2014-03-03 10:06:36 -05:00
Rejeesh Kutty
ddac1a8834
added common board files
2014-02-28 21:17:01 -05:00