Commit Graph

6491 Commits (d300b9c55c6d8a1a2233d46d1b6f42274ecf2e33)

Author SHA1 Message Date
Laez Barbosa d300b9c55c SPI Engine: Formatting on spi_engine_offload
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
2024-01-17 09:11:24 -03:00
Laez Barbosa d45be68ac4 SPI Engine: edge-based trigger
Previous level-based trigger could cause issues in some low
sampling rate setups. This commit changes it to edge-based.

Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
2024-01-17 09:11:24 -03:00
Iulia Moldovan b45e7a7313 Replace other master branch references to main
* README.md
* adi_regmap_xcvr.txt
* build_hdl.rst
* hdl_coding_guideline.rst
* data_offload/README.md

Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2024-01-16 16:48:45 +02:00
Iulia Moldovan 68461110aa Replace link in license header from master to main
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2024-01-16 16:48:45 +02:00
Jorge Marques 107b043550
library: jesd204: Fixup Vivado exiting with error (#1243)
The lack of the create_xgui_files causes Vivado to exit with an error
when running multiple Vivado instances (parallel make case)

Signed-off-by: Jorge Marques <jorge.marques@analog.com>
2024-01-16 12:43:03 +00:00
PIoandan d4f33da416
docs: Add ad738x documentation (#1240)
docs/projects/ad738x_fmc: Add ad738x_fmc project documentation

Signed-off-by: Ioan-daniel Pop <Pop.Ioan-daniel@analog.com>
2023-12-21 11:58:16 +02:00
caosjr bad1d03678
spi_engine: Fixup param ranges and CPHA info (#1239)
Set validation ranges for DATA_WIDTH and NUM_OF_CS for the expected
min/max values in the verilog source code.
Also, fix swapped description for CPHA in the documentation.

Signed-off-by: Carlos Oliveira <caosjr8@gmail.com>
2023-12-18 10:52:26 -03:00
AndreiGrozav 870b27d3d3 axi_pwm_gen: Update ttcl constraints
Signed-off-by: AndreiGrozav <andrei.grozav@analog.com>
2023-12-15 15:03:07 +02:00
AndreiGrozav e0fc09fc9e axi_pwm_gen: Start, Stop fix
Previously when issuing a load_config, each pwm channel
was stopped in its tracks and waited for an external sync,
if that was active, or load_config release.
The desired behaviour is to wait for the pwm channels to finish
their events from the current period, before a new aligned start.
Also, the first positive edge of each pulse was initiated only
in the second pwm channel period.
This niche behaviours have not affected any functionality in the
long term alignments for current setups.

Signed-off-by: AndreiGrozav <andrei.grozav@analog.com>
2023-12-15 15:03:07 +02:00
AndreiGrozav e7dd5ce394 axi_pwm_gen: Offset mecanism fix
When leaving the offset equal to zero for a pwm
channel. That pwm channel was not waiting for all
channels to get in sync after a load config.

Signed-off-by: AndreiGrozav <andrei.grozav@analog.com>
2023-12-15 15:03:07 +02:00
Alin-Tudor Sferle 119d4e43a3 axi_pwm_gen: Add support for 16 channels
Signed-off-by: Alin-Tudor Sferle <Alin-Tudor.Sferle@analog.com>
Signed-off-by: AndreiGrozav <andrei.grozav@analog.com>
2023-12-15 15:03:07 +02:00
Liam Beguin 887ffac0ed
scripts: Parallel build with pattern rules (#1202)
Drop shell for loops in favor of makefile pattern rules,
so make can run targets in parallel using -j.
This doesn't affect Vivado's own settings.

As a benchmark, 12th Gen Intel(R) Core(TM) i9-12900H 5GHz(max):
	$ make -C projects/adrv9009/zcu102/ clean-all
	$ time make -C projects/adrv9009/zcu102/ -j$CORES lib
CORES=1:
	real    9m27.223s
	user    9m2.556s
	sys     0m32.358s
CORES=8:
	real    1m54.639s
	user    16m26.512s
	sys     1m2.317s
i.e. about 5 times faster to build IP core dependencies.

Signed-off-by: Liam Beguin <liambeguin@gmail.com>
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
2023-12-14 17:27:23 +00:00
Jorge Marques 940c3ccd35 docs: Add component diagram generator
Replaces Symbolator with custom component diagram generator for more
reliable diagrams.
It uses the IP-XACT file, if it is not found, a placeholder is added
instead.

Signed-off-by: Jorge Marques <jorge.marques@analog.com>
2023-12-13 10:38:29 -03:00
Jorge Marques 9f4d5ff71f docs: General improvements
Import aiohttp and asyncio only when needed.
Better warning for unknown signals, params.
Use pattern matching in regmap parsing.
Fixup bundle count.
Add lists clarification to guidelines.
Enforce #1229 rules.
Clean-up Makefile.
Use non-breaking hyphen.

Signed-off-by: Jorge Marques <jorge.marques@analog.com>
2023-12-13 10:38:29 -03:00
AndreiGrozav 39b2a2b8bb axi_dac_interpolate: Improve the ctrl logic
1. Simplify the control logic by adding a state machine.
The improvements are on code readability and reliability.

2.Add a flush feature which can be used to clean the data from the DMA fifo.
This is useful when the DMA is programmed in cyclic mode and
data transmission is stopped by dma_transfer_suspend flag
The software intervention is reduced at setting the flag(dma_flush_en).
Flushing can also be done when activating the raw value with dma_flush_en active.

3. Add raw value support. Through this changes a user can set
the dac output to a fixed predefined value in the following two cases:
  1. direct, without using the dma.
  2. with dma, as a hold value. The fixed value will be kipped after a cyclic
buffer is stopped by axi_dac_interpolate, through dma_transfer_suspend
register/signal.
The raw value ca be set and transmitted independently on each channel.
The predefined value is stored in reg 0x19(0x64). For more details se
the documentation available at
https://wiki.analog.com/resources/fpga/docs/axi_dac_interpolate
2023-12-12 16:51:05 +02:00
AndreiGrozav 6998cc99b4 m2k: Remove dac last_sample_hold control
axi_dac_interpolate - Remove last sample hold control
axi_ad9963 - Remove last sample hold control and set as default the
last sample hold functionality plus code optimization changes.
2023-12-12 16:51:05 +02:00
PIoandan 06201d5ee1
docs: Add ad5766 documentation (#1227)
docs: Add ad5766_sdz documentation

Signed-off-by: Ioan-daniel Pop <Pop.Ioan-daniel@analog.com>
2023-12-12 12:12:47 +02:00
cristianmihaipopa c1e0698719
AD9434: Zed porting and documentation (#1210) 2023-12-07 15:18:59 +02:00
Ionut Podgoreanu 9f2a03f29d arradio: Enable the scatter-gather DMA core
Signed-off-by: Ionut Podgoreanu <ionut.podgoreanu@analog.com>
2023-12-04 14:34:33 +02:00
Ionut Podgoreanu 7a28a69061 fmcomms2: Enable the scatter-gather DMA core
Signed-off-by: Ionut Podgoreanu <ionut.podgoreanu@analog.com>
2023-12-04 14:34:33 +02:00
Ionut Podgoreanu b3c58abcdc docs: Include the DMA SG documentation
Signed-off-by: Ionut Podgoreanu <ionut.podgoreanu@analog.com>
2023-12-04 14:34:33 +02:00
Ionut Podgoreanu 2687bbc02e util_hbm: Add the SG interface in DMA instances
Signed-off-by: Ionut Podgoreanu <ionut.podgoreanu@analog.com>
2023-12-04 14:34:33 +02:00
Ionut Podgoreanu f41391fa93 axi_dmac: Add support for DMA Scatter-Gather
This commit introduces a different interface to submit transfers, using
DMA descriptors.

The structure of the DMA descriptor is as follows:

struct dma_desc {
    u32 flags,
    u32 id,
    u64 dest_addr,
    u64 src_addr,
    u64 next_sg_addr,
    u32 y_len,
    u32 x_len,
    u32 src_stride,
    u32 dst_stride,
};

The 'flags' field currently offers two control bits:
- bit 0: if set, the transfer will complete after this last descriptor
  is processed, and the DMA core will go back to idle state; if cleared,
  the next DMA descriptor pointed to by 'next_sg_addr' will be loaded.
- bit 1: if set, an end-of-transfer interrupt will be raised after the
  memory segment pointed to by this descriptor has been transferred.

The 'id' field corresponds to an identifier of the descriptor.

The 'dest_addr' and 'src_addr' contain the destination and source
addresses to use for the transfer, respectively.

The 'x_len' field contains the number of bytes to transfer,
minus one.

The 'y_len', 'src_stride' and 'dst_stride' fields are only useful for
2D transfers, and should be set to zero if 2D transfers are not
required.

To start a transfer, the address of the first DMA descriptor must be
written to register 0x47c and the HWDESC bit of CONTROL register must
be set. The Scatter-Gather transfer is queued similarly to the simple
transfers, by writing 1 in TRANSFER_SUBMIT.

The Scatter-Gather interface has a dedicated AXI-MM bus configured for
read transfers, with its own dedicated clock, which can be asynchronous.

The Scatter-Gather reset is generated by the reset manager to reset the
logic after completing any pending transactions on the bus.

When the Scatter-Gather is enabled during runtime, the legacy cyclic
functionality of the DMA is disabled.

Signed-off-by: Ionut Podgoreanu <ionut.podgoreanu@analog.com>
2023-12-04 14:34:33 +02:00
LBFFilho 0f87d845d3
SPI Engine: Add execution delay documentation (#1230)
* SPI Engine: Add execution delay documentation

Add documentation for the different delays on the command path and
data path, including communication between submodules and instruction
execution overhead.

Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
2023-11-28 18:08:51 -03:00
cristianmihaipopa 6a6e1f97f9
AD719x: Documentation (#1211)
docs/projects/ad719x_asdz: Add documentation for AD719x
2023-11-27 13:27:55 +02:00
StancaPop 9dfd00018a
docs: Improve consistency (#1229)
* docs: Improve consistency

The following rules have been implemented:
1. Tables/lists should contain only the carriers that we support for
   that reference design.
2. Hexadecimal addresses should be written in caps and separated
   by an underscore (eg. 0x9C4A_0000).
3. Block diagrams should contain subtitles only if there are at
   least two different diagrams.
4. The GPIOs should be listed in descending order and should have
   the number of bits specified next to their name.
5. All the source code links references should contain the project
   name.
6. The infrastructure documentation, if exists, should be listed
   after the IP list.
2023-11-27 12:53:21 +02:00
Stanca Pop 679d8e71ab docs: Add ad469x_fmc doc 2023-11-20 16:57:35 +02:00
Stanca Pop e626d80b99 docs/common: Remove default branch 2023-11-20 15:11:09 +02:00
Stanca Pop de2dbc5a56 docs: Fix tables consistency 2023-11-20 15:11:09 +02:00
Iulia Moldovan 0d948816c3 adi_env.tcl: Update Quartus Pro version to 23.2.0
* The version is set to be 23.2.0 because this is what Quartus returns
   as value when running the --version command
 * Still, Quartus has as installation path "intelFPGA_pro/23.2" and not
   the version which contains an additional ".0"

Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-11-20 11:28:39 +02:00
Iulia Moldovan 811dccedaf .github/workflows: Rename branch name for GitHub actions
* Rename the branch on which the actions are run on, from master to
   main

Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-11-17 12:56:26 +02:00
StancaPop c0ffdefe9d docs: Add adaq7980 documentation 2023-11-16 16:45:51 +02:00
Jorge Marques ed0f496d56
docs: flatten images paths, toctree and images guidelines (#1222)
Recommend storing images like any other artifact: in a hierarchical
manner, without "images" subfolders.
This is intended to avoid dangling artifacts when projects are moved,
renamed, or deleted.
Recommend overwriting the page title with a shorter title in the
toctree, so the navigation bar doesn't overflow or get too cluttered.
Add acostina to CODEOWNERS

Signed-off-by: Jorge Marques <jorge.marques@analog.com>
2023-11-15 12:13:26 -03:00
Ramon Cristopher Calam 12495eb282
docs: Edits on Build an HDL Project section of the user guide documentation (#1204)
* user_guide/build_hdl: Text rephrasing and proof reading.

---------

Signed-off-by: Ramon Cristopher Calam <ramoncristopher.calam@analog.com>
2023-11-15 09:01:36 +08:00
StancaPop 75c6560567 docs/ad7616: Remove duplicated info 2023-11-14 09:56:54 +02:00
Jorge Marques c66cc5e79a
docs: links, drop part, fixups, codeowners
Drop part role, use generic adi instead for root adi domain links.
For future reference, the snipped used was:
find ./docs/projects -type f -exec sed -i 's/:part:/:adi:/g' {} \;
Drop Containerfile.
Add option to validate links status (e.g. 200, 404), intended mostly for CI
use to check if a page has disappeared from the internet.
Validate links uses coroutines to launch multiple tasks concurrently,
but do it in bundles to avoid being rate limited.
Fixup regmap styling.
Add imoldovan, jmarques, spop, lbarbosa as docs codeowners.
Remove branch field for links to the hdl repo.
Change git role to display full path.
Fixup ZedBoard link label, remove IP List, add SYSID_ROM dokuwiki link
in ad716_sdz project.

Signed-off-by: Jorge Marques <jorge.marques@analog.com>
2023-11-13 15:42:46 +00:00
StancaPop 0e0e1e4655 docs/projects/ad7616_sdz: Update block diagrams 2023-11-09 14:43:20 +02:00
StancaPop 17d3baf417 ad7616_sdz: Add axi_clkgen 2023-11-09 14:43:20 +02:00
Stanca Pop f1f3968485 ad7616_sdz: Remove zc706 support 2023-11-09 14:43:20 +02:00
Stanca Pop 3446cc2100 ad7616_sdz: Add fmc pinout 2023-11-09 14:43:20 +02:00
Stanca Pop d97550fa71 ad7616_sdz: Use SPI Engine for serial mode
This commit makes the following changes:
Add SPI Engine for serial mode
Add SER_PAR_N build parameter, set default 1 for serial
Fix irq consistency in ad7616_bd.tcl
Fix regmap and offload names
Fix system_top.v GPIOs
2023-11-09 14:43:20 +02:00
Stanca Pop 9ba84cf7c0 axi_ad7616: Remove serial dependencies 2023-11-09 14:43:20 +02:00
Alin-Tudor Sferle 03c4276a2b axi_ad7606x: Add the correct IP's name
Signed-off-by: Alin-Tudor Sferle <Alin-Tudor.Sferle@analog.com>
2023-11-07 15:00:06 +02:00
PIoandan a806a6f6ec
projects: Add missing sysid IP (#1172)
* Projects: Add missing sysid IP

* Added make parameters for the sysid ip for the projects: ad9209_fmca_ebz/vck190, ad9213_dual_ebz/s10soc and adrv9009/s10soc

Signed-off-by: Pop Ioan Daniel <pop.ioan-daniel@analog.com>
2023-11-03 09:52:13 +02:00
Stanca Pop a09ee9d481 docs/projects/ad7616_sdz: Add ad7616_sdz project documentation 2023-11-02 14:50:42 +02:00
LBFFilho becc035ba9
SPI Engine: Fixed delay behaviour on Chip-Select and Sleep instructions (#1200)
Fixed wrong behaviour on chip select instruction:
- previously, a sleep time happened before the chip select change
- the intended behaviour was for another sleep time, of equal amount, to happen after the chip select change as well
- additionally, the counter logic implementation was creating an additional factor of 2 on the sleep time

All of the above points were fixed. The changes introduced also fix another issue where the sleep instruction was likewise happening with a duration larger than intended by a factor of 2


Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
2023-10-30 09:52:04 -03:00
kylex 365933542d
scripts/adi_board.tcl: use axi_interconnect for HP ports on Zynq-7000 family
Commit 5db7574 switched ad_cpu_interconnect from SmartConnect to
AXI Interconnect for Zynq-7000 family SoC. This commit does the
same for ad_mem_hpx_interconnect.

Signed-off-by: Alexander Vickberg <wickbergster@gmail.com>
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
2023-10-30 09:48:32 -03:00
Iulia Moldovan f81532d1d7 projects: Update Readme.md for ad9783_ebz & ad9081/ad9082_fmca_ebz
* Now the Readme.md points to the GitHubIO documentation

Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-10-26 09:13:36 +03:00
Iulia Moldovan f548c422b8 docs/projects/ad9783 & images: Add ad9783_ebz project doc
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-10-26 09:13:36 +03:00
Iulia Moldovan c301f4f44e docs/projects/ad9081 & images: Add ad9081_fmca_ebz project doc
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-10-26 09:13:36 +03:00