* Added header license for the files that didn't have
* Modified parentheses
* Removed extra spaces at the end of lines
* Fixed parameters list to be each parameter on its line
* Deleted lines after endmodule and consecutive empty lines
* Fixed indentation
Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
This patch contains an initial effort to support the Stratix 10
architecture in our JESD204 framework.
Several instances were updated, doing simple context switching using the
DEVICE_FAMILY system parameter:
- xcvr_reset_control
- lane PLL (ATX PLL)
- link PLL (fPLL)
- native XCVR instance
Apart from the slightly different parameters of the instances above,
there were small differences at the reconfiguration Avalon_MM interface.
The link_pll_reset_control is required just for Arria10, so in case of
Stratix10 it isn't instantiated.
In Stratix 10 architecture there are several additional ports of the
xcvr_reset_control module that must be connected to the native XCVR
instance or tied to GND.
The following xcvr_reset_control ports were defined and connected to the
XCVR:
- rx|tx_analogreset_stat
- rx|tx_digitalreset_stat
- pll_select
* jesd204b: add bonding clocks feature (fix for some routing issues)
* intel/adi_jesd204: bonding clock feature invisible in QSYS GUI if number of lanes is less than 6
* intel/adi_jesd204: clock network option renamed according to intel documentation
* intel/adi_jesd204: Hide BONDING_CLOCKS_EN parameter in RX mode
Co-authored-by: István Csomortáni <Csomi@users.noreply.github.com>
In Subclass 1 mode an external device clock (core clock) is used,
instead of the PCS output clock, to drive the link and transport layer.
Define an additional parameter, which can be used to enable clock input
port for the PHY module, which can be used as rx|tx_coreclkin source.
Iulia Moldovan
Iacob_Liviu
Adrian Costina
stefan.raus
Laszlo Nagy
Istvan Csomortani
cycollineau