Commit Graph

6491 Commits (d300b9c55c6d8a1a2233d46d1b6f42274ecf2e33)

Author SHA1 Message Date
Ionut Podgoreanu 567be16bf6 library/jesd204: Update the script which computes the TPL width to be able to assign custom values 2022-08-25 12:35:42 +03:00
Ionut Podgoreanu 5a06f186ae ad9081_fmca_ebz/common: Use the script to compute the TPL width 2022-08-25 12:35:42 +03:00
AndreiGrozav f955fbc6c0 adi_pd.tcl: Fix sysid branch string
For some newer versions of git where by default color.ui=always.
The colored string captured can result in some special characters
(ASCI escape codes for coloring the terminal output) before and after the string.
e.g:
$ git branch > test.txt
$ vim test.txt
"
* ^[[32mmaster^[[m
  dev_new_device^[[m"

The above escape codes will mess up a terminals color scheme  when this
information is read from sysid and displayed on a terminal.

Use --no-color flag to fix this issue.
2022-08-25 11:36:25 +03:00
Iulia Moldovan 388611866a projects: Fix some Makefiles
* ad9082_fmca_ebz/vcu118
 * dac_fmc_ebz/vcu118

Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
2022-08-25 09:35:55 +03:00
ladace cf4e1b79cf
scripts:adi_env: Change the default version of Quartus Standard to 21.1 (#996)
New version of Quartus Standard for de10nano and sockit  was changed
to 21.1.

Signed-off-by: Liviu Adace <liviu.adace@analog.com>

Signed-off-by: Liviu Adace <liviu.adace@analog.com>
2022-08-24 17:01:06 +03:00
PopPaul2021 cc18f90579
Added axi_ad7768 IP Core (#989)
* projects/ad7768evb: Initial commit with axi_ad7768 IP

* library/axi_ad7768: Initial commit for AD7768/AD7768-4
2022-08-24 16:57:14 +03:00
LIacob106 a824bbfdbe library/scripts/adi_ip_xilinx.tcl: remove duplicate adi_env.tcl source
Signed-off-by: LIacob106 <liviu.iacob@analog.com>
2022-08-23 17:55:27 +03:00
ladace 4307e3071f
scripts:adi_env: Change the default version of Quartus Pro to 21.4 (#988)
New version of Quartus Pro for A10SOC, A10GX and S10SOC was changed
to 21.4. Is known that some projects will not build anymore due to
timming violations.
2022-08-18 17:08:29 +03:00
Iulia Moldovan e02d31cdfd scripts: Set required Vivado version only in adi_env.tcl
Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
2022-08-18 15:41:58 +03:00
Iulia Moldovan dde37124a4 scripts: Update Vivado version to 2021.2
Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
2022-08-18 15:41:58 +03:00
Ionut Podgoreanu 214cf5896e library/common: Enable automatic logging of simulation output 2022-08-10 12:00:15 +03:00
Ionut Podgoreanu 79579f65df library/common: Update the packing IPs to be more generic 2022-08-10 12:00:15 +03:00
PopPaul2021 0595f93452
AD777x support for ZedBoard and DE10Nano (#937)
* library/common: Ad adc_status_header, adc_crc_err and adc_crc_enable.

* library/axi_ad777x: Initial commit for Xilinx and Intel

* projects/ad777x_ardz: Initial commit for ZedBoard and DE10Nano
2022-08-10 11:29:05 +03:00
Laszlo Nagy ab29f21f7a axi_ltc2387: Update data formatter instance to use bits instead of octets 2022-08-08 14:22:24 +03:00
Laszlo Nagy d8a6e81c7e jesd204/ad_ip_jesd204_tpl_adc: Fix data formater for N'=12 if DMA interface is also 12 2022-08-08 14:22:24 +03:00
Iacob_Liviu 482f0489a3 scripts: Merge adi_env.tcl into a single file
Move the new adi_env.tcl file from hdl/projects/scripts into hdl/scrips
2022-08-08 13:52:54 +03:00
Filip Gherman 929f80cd31 library/jesd204: Updated jesd to support more lanes
Modified the maximum number of supported lanes up to 32 lanes for every JESD layer

Signed-off-by: Filip Gherman <Filip.Gherman@analog.com>
2022-08-04 13:10:53 +03:00
Laszlo Nagy d48b1bcdce ad9081_fmca_ebz/vck190: Expose ref clock parameter 2022-08-04 09:52:57 +03:00
Laszlo Nagy 78333b2c90 ad9081_fmca_ebz/common/versal_transceiver: Separate lane rates for Tx and Rx 2022-08-04 09:52:57 +03:00
Laszlo Nagy 3379dd3bdb ad9082_fmca_ebz/zcu102: Make JESD_MODE overwritable 2022-08-04 09:50:18 +03:00
Laszlo Nagy 7a48f1beb9 util_do_ram: Fix Rx path for interrupted transfers
When capture length is not programmed the DMA will interrupt the
transfer once it received all the samples he was set in its descriptor,
this case must be handled by resetting the read process and returning
an end of transfer (eot) to the data offload control logic.
2022-08-04 09:45:52 +03:00
Laszlo Nagy 1d4b27ea8c util_axis_fifo_asym: Fixes for simulation
Initialization of regs was not executed in always(*) blocks since
the block is not triggered due missing inputs.
2022-08-04 09:45:52 +03:00
Laszlo Nagy 4982104982 data_offload: Fix Tx bypass
Tx path was gated by the FSM also in bypass mode. This must be avoided
since the bypass mode should be independent of the FSM.

Write to bypass fifo only when bypass is enabled
2022-08-04 09:45:52 +03:00
Liviu.Iacob 54a22d036c adi_pd.tcl: Fix git_clean_string logic 2022-08-02 17:11:49 +03:00
Sergiu Arpadi 94c4a291a7 cn0561_coraz7s: Fix gpio connections 2022-08-02 17:11:19 +03:00
Sergiu Arpadi bb3027995a sysid: Add sysid support for de10nano
make adv7513

make 0540
2022-08-02 14:15:34 +03:00
Laszlo Nagy c748b3bbc7 ad9082_fmca_ebz/zc706: Fix parameters
Match default parameters for L=4 M=8 mode with 10Gbps.
The L=8 M=4 would require lane rate of 15Gbps that is not supported on
zc706.
2022-08-01 16:40:03 +03:00
Laszlo Nagy aae7971689 ad9082_fmca_ebz/vcu118: Fix default lane rate parameter 2022-08-01 16:40:03 +03:00
Laszlo Nagy aed7032e0c ad9082_fmca_ebz/zcu102: Fix default lane rate parameter 2022-08-01 16:40:03 +03:00
Laszlo Nagy bdaa0f086b data_offload: Increase bypass FIFO size 2022-08-01 12:47:26 +03:00
Laszlo Nagy 2b274f945f ad9081_fmca_ebz: Reset cpack with Rx data offload 2022-08-01 12:47:26 +03:00
Filip Gherman d48ab915a5 vcu128: Connect sys_mb_rstgen/ext_reset_in accordingly
Signed-off-by: Filip Gherman <Filip.Gherman@analog.com>
2022-07-29 20:05:08 +03:00
LIacob106 472f41ad2c ad_ip_jesd204_tpl_adc_hw.tcl: Add 14 bit option for converter resolution 2022-07-25 14:14:28 +03:00
alin724 6aa899f161 scripts/adi_project_xilinx.tcl: Add new constraints file support 2022-07-20 14:36:04 +03:00
alin724 9864d96096 Merge CN0506 projects into a parameterized one 2022-07-20 14:36:04 +03:00
Iulia Moldovan 6113f3d70f action: Add workflow for github action to run check_guideline.py
Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
2022-06-28 18:06:56 +03:00
Iulia Moldovan 1014a0de78 script: Add Py script to check for guideline rules & README.md
Added readme_check_guideline.md along with the check_guideline.py
to explain the usage of this and to show how it should be used.

Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
2022-06-28 18:06:56 +03:00
Iulia Moldovan 961ebe0cc2 projects: Update .v files according to guideline
Deleted lines after endmodule and consecutive empty lines.
Modified parentheses, extra spaces.
Fixed indentation.
Fixed parameters list to be each parameter on its line.

Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
2022-06-28 18:06:56 +03:00
Iulia Moldovan 0c0617d49e libraries: Update modules according to guideline
* Added header license for the files that didn't have
* Modified parentheses
* Removed extra spaces at the end of lines
* Fixed parameters list to be each parameter on its line
* Deleted lines after endmodule and consecutive empty lines
* Fixed indentation

Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
2022-06-28 18:06:56 +03:00
Iulia Moldovan 521476a8d4 lint: Update to run only in PRs. Change version for checkout action
* Updated action to run only in PRs on master branch, on library/ and
  projects/ paths
* Edited the text for the printed warnings
* Updated the version for the checkout action from v2 to v3

Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
2022-06-28 12:45:29 +03:00
Laszlo Nagy 171daab8f2 ad9081_fmca_ebz: a10soc: Update resistor change comment
A board rework is required so the clocks, chip selects or sync signal reach the part correctly.  Without this the link will not come up.
2022-06-21 14:19:58 +03:00
Liviu.Iacob da18ecccda .gitignore: ignore files generated by Quartus & Platform Designer
Added the files generated by Quartus Pro 21.2, 20.1 and Platform Designer for each of the versions. The files added are generated and removed by make.

Signed-off-by: Liviu.Iacob <liviu.iacob@analog.com>
2022-06-09 11:32:10 +03:00
Laszlo Nagy a8174ac038 ad_quadmxfe1_ebz/vcu118/system_project.tcl: Update comments
Update PLL selection docs.
2022-06-08 15:35:47 +03:00
ladace 6525a37375
ad_fmclidar1_ebz:a10soc Fixed problems with SPI communication with AD9094 (#951)
Now CPH and CPOL are set to 1, also the SPI clock is set to 10MHz

Signed-off-by: Liviu Adace <liviu.adace@analog.com>
2022-06-06 13:00:45 +03:00
PopPaul2021 4f4825a3df
projects:daq2:common: fix adi_tpl_jesd204_rx_create error. (#952)
(\ character has to be removed or a blank line inserted before ad_ip_parameter)
Fix for : 0b8585a6f commit.
2022-06-06 08:53:07 +03:00
Liviu.Iacob 5c9f006ab2 .gitignore: Fix to ignore imbricated bd.tcl files too
Fix gitignore commit 6a6c5ac that did not ignore imbricated bd files.
Signed-off-by: Liviu.Iacob <liviu.iacob@analog.com>
2022-06-03 15:58:45 +03:00
PopPaul2021 0b8585a6f1
PN mismatch DAQ2, DAQ3 and FMCJESDADC1 fix (#950)
The AD9680 is a dual 14-bit ADC.
Software sets the output format to offset binary before performing the PN tests.
2022-06-02 14:09:36 +03:00
Ionut Podgoreanu f957d81db1 ad9083_evb_bd: Connect util_ad9083_rx_cpack reset to adc_rst 2022-05-27 09:20:09 +03:00
Filip Gherman 1ae375f4fb ad_quadmxfe1_ebz/vcu118: Change drp clock source used for jesd204_phy
- Added an utility buffer in order to generate the 50Mhz DRP clock.
- 'addn_ui_clockout4' will be used to generate the higher frequency 'sys_mb' clock for Microblaze.

Signed-off-by: Filip Gherman <Filip.Gherman@analog.com>
2022-05-27 00:48:34 +03:00
Filip Gherman 5ad9dfd6c0 vcu118: Increase Microblaze performance and clock frequency
Increased the Microblaze performance for the VCU118 carrier:
- Increased the size of Instruction Cache and Data Cache to 64kB

Increased the Microblaze clock frequency:
- Using the DDR4 Controller to generate a new sys_mb_clk of 214 MHz to drive all the Microblaze interfaces at higher frequencies

Signed-off-by: Filip Gherman <Filip.Gherman@analog.com>
2022-05-27 00:48:17 +03:00