Istvan Csomortani
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1c23cf4621
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all: Update verilog files to verilog-2001
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2017-04-13 11:59:55 +03:00 |
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Istvan Csomortani
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81a1c21553
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util_pmod_adc: Reset line changed to active low reset.
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2015-09-30 12:33:46 +03:00 |
Adrian Costina
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233cc111d2
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util_pmod_adc: Used generated clock for the ADC SPI. Works by default at 6.25MHz
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2015-05-05 23:33:13 +03:00 |
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Istvan Csomortani
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d02c21b426
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util_pmod_adc: General update
Redesign the state machine, rename constant and variable names, add notes and description.
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2015-02-04 14:49:16 +02:00 |
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Istvan Csomortani
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659e0cca4e
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cftl_cip: Initial check in.
Project cftl_cip supports the following Circuits from the Lab pmods:
+ EVAL-CN0350-PMDZ
+ EVAL-CN0335-PMDZ
+ EVAL-CN0336-PMDZ
+ EVAL-CN0337-PMDZ
Note: Additional testing needed!
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2015-01-23 18:29:32 +02:00 |