1c23cf4621
all: Update verilog files to verilog-2001
2017-04-13 11:59:55 +03:00
b0f90bd0e8
daq1/cpld: Read interface fix
2016-03-04 20:28:24 +02:00
7e607957ee
daq1.cpld: Prevent the spi_counter to roll over.
2016-03-04 20:28:22 +02:00
262a42c676
daq1/cpld: Update CPLD_VERSION value
2016-03-04 20:28:20 +02:00
9439862301
daq1/cpld: Update CPLD
...
Change to control line fpga_to_cpld to cpld_to_fpga, this is not a functional change.
2016-03-04 20:28:18 +02:00
5518c47ca4
daq1_cpld: Set Input and tristate I/O termination mode to FLOAT
2016-02-15 19:27:59 +02:00
051ac307e6
daq1_cpld: Do not forward the first eight clock cycles of fmc_spi_sclk to sclk
2016-02-15 19:26:58 +02:00
9370246cfa
daq1: Fix bugs on CPLD design
...
Fix the CSN forwarding.
2016-02-12 16:59:09 +02:00
5ed2c0b599
daq1: Update CPLD constraints file
2016-02-12 16:54:36 +02:00
aa2ff0223a
daq1: Update CPLD design
...
+ SPI counter counts on negative edge of the SPI_CLK
+ Shift register for read, shifting MSB first
+ Fix write access logic
+ Update the internal register addresses
2016-02-12 14:45:18 +02:00
aa77af6bdf
daq1_cpld: Add ISE project file
...
This file, along with the project source files, is sufficient to open and implement in ISE Project Navigator.
2016-01-21 18:05:59 +02:00
8c69c9d2ce
daq1_zc706 : Update the project
...
+ Add AD9684 to the block design
+ Update the IO definitions
+ Update the CPLD design
+ Add 3wire SPI logic
2016-01-19 11:20:35 +02:00
02cc926275
daq1: Add CPLD logic and IO constraints
2016-01-04 18:10:46 +02:00
Istvan Csomortani