Adrian Costina
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d40db9e204
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adrv9009zu11eg: Added additional GPIOs and CS to the GPIO expander
This should integrate seamlessly with SYNCHRONA14
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2022-04-01 10:24:04 +03:00 |
PopPaul2021
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c71e5de928
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zcu102: ad_fmclidar1_ebz, fmcomms5, fmcomms8 (#811)
adrv2crr_fmc: adrv9009zu11eg
adrv2crr_xmicrowave: adrv9009zu11eg
The IBUFGDS primitive is deprecated in UltraScale devices.
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2021-11-22 08:09:46 +02:00 |
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Adrian Costina
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591a23156b
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Makefiles: Update header with the appropriate license
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2021-09-16 16:50:53 +03:00 |
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Adrian Costina
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4cf53f373b
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Revert "adrv9009zu11eg: Integrate data_offload"
This reverts commit 78999e154e.
The integration wasn't properly tested
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2021-08-19 21:43:09 +03:00 |
Istvan Csomortani
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78999e154e
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adrv9009zu11eg: Integrate data_offload
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2021-08-06 11:55:24 +03:00 |
Sergiu Arpadi
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a1773c661c
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adrv9009zu11eg_crr: Update spi
Add two more CS signals to P25 connector
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2021-03-10 10:53:11 +02:00 |
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Sergiu Arpadi
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6f2f2b8626
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makefile: Regenerate make files
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2021-01-20 01:02:56 +02:00 |
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sergiu arpadi
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acbbd4636a
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sysid: Upgrade framework, header/ip are now at 2/1.1.a
Unify tcl scripts; rename adi_pd_intel.tcl to adi_pd.tcl
add git branch to internal use area; update log prints;
update xilixn projects; fix cn0506 sysid script;
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2021-01-20 01:02:56 +02:00 |
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Istvan Csomortani
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e41ba7f6f5
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adrv9009zu11eg: Use adi_project_create instead of adi_project
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2021-01-15 15:26:43 +02:00 |
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Istvan Csomortani
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2799777657
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adrv9009zu11eg/adrv2crr_fmc: Fix hmc7044_car_gpio connections
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2020-11-11 07:07:29 -05:00 |
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Adrian Costina
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9093a8c428
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library: Move ad_iobuf to the common library, as it's not Xilinx specific
Updated all system_project and Makefiles
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2020-11-02 16:13:35 +02:00 |
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Sergiu Arpadi
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d8ab27b2af
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sysid: Remove cstring init string
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2020-09-30 19:12:24 +03:00 |
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Adrian Costina
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c4b94fc564
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adrv9009zu11eg: Add S JESD204 parameter for the projects
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2020-02-18 11:19:02 +02:00 |
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Adrian Costina
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645696e5b4
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adrv9009zu11eg: Extend SPI connection to the PL HD PINS expansion
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2020-02-18 11:19:02 +02:00 |
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Adrian Costina
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09ad67bfd7
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adrv9009zu11eg: Make the project more parametrizable
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2019-12-04 14:59:18 +02:00 |
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Adrian Costina
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0cb5c0bdaf
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adv9009zu11eg: Update FPGA to -2. Update DDR4 clock frequency
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2019-11-27 16:27:44 +02:00 |
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Adrian Costina
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dfe3258a4f
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adrv9009zu11eg: Add axi_sysid
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2019-11-19 10:29:57 +02:00 |
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Adrian Costina
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a589a2c7eb
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adrv9009_zu11eg_som: Change design partitioning
Create a structure similar with ADRV936x projects
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2019-11-14 15:25:23 +02:00 |