Commit Graph

435 Commits (d4c9f1e9f10b1525c9897677f65da84770ac11d6)

Author SHA1 Message Date
Rejeesh Kutty 0b3b1e6c76 kcu105- remove ethernet delay ctrl false path 2017-05-19 11:21:36 -04:00
Rejeesh Kutty f3959cb5b9 zcu102- 2016.4 updates 2017-05-18 14:17:20 -04:00
Rejeesh Kutty d507cd0c9a quartus optimization for frequency 2017-05-18 11:34:29 -04:00
Rejeesh Kutty d10faabc3f a10soc- 16.1- hsp sdram reset 2017-05-17 16:30:37 -04:00
Rejeesh Kutty f8f7bdd6a6 a10soc- fix version check 2017-05-17 16:26:28 -04:00
AndreiGrozav 70e3dd00ff scripts: Update required tool versions 2017-05-17 16:45:20 +03:00
Istvan Csomortani 9055774795 all: Update license for all hdl source files
All the hdl (verilog and vhdl) source files were updated. If a file did not
have any license, it was added into it. Files, which were generated by
a tool (like Matlab) or were took over from other source (like opencores.org),
were unchanged.

New license looks as follows:

Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.

Each core or library found in this collection may have its own licensing terms.
The user should keep this in in mind while exploring these cores.

Redistribution and use in source and binary forms,
with or without modification of this file, are permitted under the terms of either
 (at the option of the user):

  1. The GNU General Public License version 2 as published by the
     Free Software Foundation, which can be found in the top level directory, or at:
https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html

OR

  2.  An ADI specific BSD license as noted in the top level directory, or on-line at:
https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
2017-05-17 11:52:08 +03:00
Rejeesh Kutty cfcb269d38 a10gx- change ddr to 1G 2017-05-15 09:32:36 -04:00
Rejeesh Kutty 63b701ccab altera- add version check 2017-05-12 15:13:29 -04:00
Rejeesh Kutty ebeebdddf0 altera- infer latest versions 2017-05-12 13:40:14 -04:00
Rejeesh Kutty c728299e71 altera- default to latest version 2017-05-12 13:25:17 -04:00
AndreiGrozav f0bc3e20ef zcu102: Automatic IP version update fix 2017-05-02 12:52:43 +03:00
AndreiGrozav cd8f4f23be zcu102: Automatic IP version update 2017-05-02 12:30:00 +03:00
Rejeesh Kutty b3ce821311 change pl ddr clock to 1G 2017-05-01 09:35:10 -04:00
Istvan Csomortani fa794520fd kc705_common/adv7511: Update IP instantiations 2017-04-21 15:03:31 +03:00
Istvan Csomortani 6ed721ee66 adrv9371/a10soc: Integrate the avl_dacfifo into project 2017-04-21 13:27:35 +03:00
Istvan Csomortani 2379514ae6 ac701_common/adv7511: Update IP instantiations
IPs are instantiated using the ad_ip_instance process, and configured
with the ad_ip_paramter process, to facilitate the tool upgrade.
2017-04-21 13:16:25 +03:00
Lars-Peter Clausen bb0021a926 common: zed/zc702/zc706/mitx045: audio_clkgen: Disable phase alignment
There is no need for the audio clock to be phase aligned to its source
clock. When phase alignment is disabled the MMCM uses an internal feedback
path without requiring external resources, so disable it.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-20 18:12:24 +02:00
Lars-Peter Clausen bfcc3696e4 common: zed/zc702/zc706/mitx045: Set audio clkgen clock source type
Depending on the configuration of the clock source type of the input clock
the clocking wizard will instantiate all kinds of buffers on the input
clock signal.

For these particular projects there is no need to add any kind of buffer
since the source is already coming from a global clock buffer.  So set the
configuration accordingly.

Avoids the following warning:
	[Opt 31-32] Removing redundant IBUF since it is not being driven by a
	top-level port. i_system_wrapper/system_i/sys_audio_clkgen/inst/clkin1_ibufg
	Resolution: The tool has removed redundant IBUF. To resolve this
	warning, check for redundant IBUF in the input design.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-20 18:12:24 +02:00
Lars-Peter Clausen 23ccc66f22 common: zc702/zc706/mitx045: audio_clkgen: Infer input clock frequency
Instead of manually specifying the input clock frequency let the core infer
it automatically. This makes it more straight forward to change the clock
frequency.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-20 18:12:24 +02:00
Lars-Peter Clausen b213567305 common: zed: audio_clkgen: Infer input clock frequency
Instead of manually specifying the input clock frequency let the core infer
it automatically. This makes it more straight forward to change the clock
frequency.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-19 16:29:09 +02:00
Adrian Costina 71394ee465 kcu105: ip automatic version update 2017-04-18 11:59:54 +03:00
Adrian Costina 942d69a30c Makefiles: Change MMU enabling parameter for altera designs from MMU to NIOS2_MMU 2017-04-18 10:57:16 +03:00
Adrian Costina 20672a3a8b mitx045: ip automatic version update 2017-04-14 17:46:25 +03:00
Adrian Costina 954037a716 microzed: ip automatic version update 2017-04-14 17:24:24 +03:00
Istvan Csomortani 1c23cf4621 all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
AndreiGrozav 627f78ec19 Ip automatic version update: common/board
- vc707
- zc702
- zed
2017-04-12 19:03:16 +03:00
Rejeesh Kutty 2535165461 xilinx- ad-ip-instance & ad-ip-parameter 2017-04-06 13:04:19 -04:00
Rejeesh Kutty 80f93e6a31 zc706- ad-ip-instance & ad-ip-parameter 2017-04-06 13:03:22 -04:00
Rejeesh Kutty deb8635854 adrv9371x/altera- gpio equivalency fix 2017-03-27 16:37:55 -04:00
Rejeesh Kutty 4a275302a0 a5soc- add ddr3 location assignments 2017-03-22 10:12:34 -04:00
Rejeesh Kutty b3f06af77a altera srf files do not work 2017-03-22 09:25:50 -04:00
Rejeesh Kutty 66a5d44a18 a5gte- add constraints for tq 2017-03-21 10:53:31 -04:00
Rejeesh Kutty 2e22ce3b62 a10gx- ignore preliminary timing model warnings 2017-03-21 10:52:28 -04:00
Rejeesh Kutty c7351f3ce3 arradio/c5soc- remove qsys files 2017-03-20 15:56:07 -04:00
Rejeesh Kutty 589e6b53d8 arradio/c5soc- qsys-script flow 2017-03-20 15:42:33 -04:00
Rejeesh Kutty b39fecadd9 altera- ignore preliminary timing messages 2017-03-20 12:48:53 -04:00
Rejeesh Kutty 7dfa8c599f arradio/c5soc- updated to new framework/16.0 2017-03-20 12:15:18 -04:00
Rejeesh Kutty 12f44ccbcc arradio/c5soc- critical warnings fix 2017-03-20 12:14:21 -04:00
Rejeesh Kutty 3fa9a30f0e a10soc/plddr4- lower mem clk to meet timing 2017-03-06 14:12:25 -05:00
Rejeesh Kutty 38a27d02f6 a10soc/plddr4- differential refclk 2017-03-06 14:11:36 -05:00
Rejeesh Kutty ec89b1a45f altera/adrv9371x- add dacfifo 2017-03-01 15:52:07 -05:00
AndreiGrozav c1be17a3af Altera a10 devices: disable warnings regarding unused channels 2017-03-01 11:32:17 +02:00
Rejeesh Kutty aad41039bd a10soc- plddr4 settings 2017-02-28 13:36:28 -05:00
Rejeesh Kutty c1aac4a9fb common: adc/dac fifo board designs 2017-02-27 16:06:39 -05:00
Istvan Csomortani 1fce57f6c3 axi_dacfifo: Redesign the bypass functionality 2017-02-23 17:32:31 +02:00
Rejeesh Kutty edd5e9570f file renamed; sed output; fingers crossed 2017-02-22 15:56:37 -05:00
Rejeesh Kutty b00dc4b195 plddr3- change to board files 2017-02-22 15:22:50 -05:00
Rejeesh Kutty 89b49d2f67 fifo- as board files 2017-02-22 15:18:50 -05:00
Rejeesh Kutty 879ed64bb6 compression flag changes 2017-02-22 15:15:53 -05:00