Lars-Peter Clausen
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77399ec7aa
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axi_logic_analyzer: Add missing reset wire declaration
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
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2017-04-18 12:17:40 +02:00 |
Adrian Costina
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8ba86cb75c
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axi_logic_analyzer: Allow changing data pins direction to output only after data is available from the DMA or if the output is set from a register for that specific pin
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2017-04-18 12:17:40 +02:00 |
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Adrian Costina
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8476d9d59a
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axi_logic_analyzer: Allow only data[0] to be used as alternative clock.
- drive all logic on clk_out instead of clk
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2017-04-18 12:17:39 +02:00 |
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Adrian Costina
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d7edd71aef
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axi_logic_analyzer: Triggering changes on valid data
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2017-03-14 15:25:00 +02:00 |
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Adrian Costina
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37a1c98c12
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axi_logic_analyzer: Switched from BUFGMUX to BUFGMUX_CTRL for glitch free clock switching
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2017-02-27 14:19:54 +02:00 |
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Adrian Costina
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6604cc7322
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axi_logic_analyzer: Initial commit
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2017-01-31 16:23:56 +02:00 |