1c23cf4621
all: Update verilog files to verilog-2001
2017-04-13 11:59:55 +03:00
c9a5057b93
library/prcfg : Split data bus to channels
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Because of the new pack/upack modules on the data path, it makes more sense to split the data interface of the PR modules into separate channels.
The top module will supports max 4 channels.
2015-10-13 11:36:45 +03:00
42874bfe81
prcfg_library: Major update
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Get rid of the QPSK symbol wrapper for now. The DMA data path is using the 2 LSB bits.
2014-11-18 10:05:52 +02:00
eb520b1f75
prcfg_qpsk: Major update
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Add a symbol wrapper to the logic. Wraps the 32 bit data to 2 bit symbols.
2014-10-31 12:10:59 +02:00
9dfbf4a9a6
prcfg: Update the prcfg logic to the new ad9361 interface
2014-08-05 17:54:37 +03:00
75e624ef15
prcfg_lib: Flop the status and mode nets
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Flop the status and mode nets in case of BIST and QPSK configurations.
2014-07-08 12:23:48 +03:00
7e5748374d
prcfg_lib: Fixed prbs generator for QPSK
2014-07-02 18:14:35 +03:00
ea22d29862
prcfg: Initial check in of PR modules
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Initial check in of the partial reconfiguraiton modules.
2014-06-05 14:58:14 +03:00
Istvan Csomortani