d66387f482
fmcjesdadc1- board qsys
2015-07-22 15:23:39 -04:00
3e2712cf18
a5gt-base: initial updates
2015-07-22 15:22:22 -04:00
64070b6f27
a5gt- base system
2015-07-22 15:04:59 -04:00
28aea82952
fmcomms2_zc702: Add SPI and GPIO interface for FREQCVT
2015-07-22 10:16:04 +03:00
b4eac232db
a10gx- move cores inside qsys
2015-07-21 11:06:45 -04:00
fcc298d837
a10gx- move cores inside qsys
2015-07-21 11:06:17 -04:00
b3102b5095
daq2/a10gx-- xcvr+base changes
2015-07-21 11:01:45 -04:00
445c4c835d
daq2-bd: xcvr components
2015-07-21 10:54:23 -04:00
08e46c5ff2
a10gx-base: data-master connections
2015-07-21 10:53:54 -04:00
97b8468819
daq2- constraints
2015-07-20 09:32:17 -04:00
1d6a77049d
daq2- base/board split
2015-07-20 09:31:57 -04:00
4b8d764852
daq2- base system modifications
2015-07-20 09:31:44 -04:00
da2e7acacb
daq2- separate base/board systems
2015-07-20 09:31:15 -04:00
2f53dc4412
daq2- board system only
2015-07-20 09:30:32 -04:00
a87b8fbf94
a10gx- base system only
2015-07-20 09:29:30 -04:00
80dc3bf92f
daq2/a10gx: remove signal tap
2015-07-16 14:59:01 -04:00
1de74c0267
fmcadc4: Changed the SPI CS address similar to previous version
2015-07-16 18:22:05 +03:00
c949482574
fmcadc4: Set explicit PCORE_ID for AD9680
2015-07-16 18:21:49 +03:00
a7da779b94
Makefile: Updated Makefiles
2015-07-16 18:19:42 +03:00
4e99a2cb01
xcvr: remove signal tap
2015-07-16 08:09:56 -04:00
7c142178dd
daq2/a10gx- axi_jesd_xcvr sysref name changes
2015-07-15 15:59:52 -04:00
ffd767deb2
daq2/a10gx- axi_jesd_xcvr sysref name changes
2015-07-15 15:59:51 -04:00
6c0ad6ede8
daq3: bsplit/ccat -- removed
2015-07-15 13:05:53 -04:00
a454b73d27
fmcjesdadc1/a5gt: split xcvr cores
2015-07-15 09:44:53 -04:00
2d8fa2024b
fmcjesdadc1/a5gt: split xcvr cores
2015-07-15 09:44:52 -04:00
226e23ca1f
fmcjesdadc1- xcvr components
2015-07-15 09:44:51 -04:00
1dcbf5e5a2
fmcomms2/zc706: Fix GPIO connections
...
Fix GPIO connections for the FREQCVT board.
2015-07-15 15:12:01 +03:00
1f7745610e
daq2- ddr updates
2015-07-14 12:46:52 -04:00
a38339a3ec
fmcomms2/rfsom: Add GPIO control for the RF card
2015-07-14 13:12:54 +03:00
ba2029a6e8
fmcomms2/rfsom: Delete trailing whitespaces from system_constr.xdc
2015-07-14 13:12:53 +03:00
a2e7fb9491
daq2/a10gx: qsys signal tap version
2015-07-13 10:07:18 -04:00
825fddd034
transceiver split up outside qsys
2015-07-10 11:45:07 -04:00
8c0d74aa90
transceiver split up outside qsys
2015-07-10 11:44:42 -04:00
e40aac9ab6
transceiver split up outside qsys
2015-07-10 11:44:22 -04:00
897c31ebbf
imageon: moved spdif_rx to DMA3 to be compatible with both zc706 and zed
2015-07-09 10:58:54 +03:00
f1dd2435b4
signal tap removed
2015-07-08 15:47:31 -04:00
c9e73b023d
signal tap removed
2015-07-08 15:46:52 -04:00
f64df40a0a
signal tap removed
2015-07-08 15:47:50 -04:00
19bf05c740
signal tap removed
2015-07-08 15:47:48 -04:00
bbf1c5b803
transceiver core added/gpio removed
2015-07-07 15:30:38 -04:00
075b1e5424
daq2/a10gx: added axi_jesd_xcvr control
2015-07-07 10:22:36 -04:00
46fa91d5be
Makefile: Update Make files
2015-07-03 18:08:57 +03:00
8c98399c37
imageon_ZC706: Add axi_spdif_rx core to the design
2015-07-03 17:48:29 +03:00
27b786e92f
imageon_loopback: Use BUFIO for the HDMI clock buffer
...
Since we are just doing a loopback all the logic is contained within the
IO bank. By using a BUFIO instead of a BUFG we avoid having to route the
clock signal from the IO bank to the middle of the FPGA and back to the IO
bank. This reduces the skew between clock and the data signals and makes
sure that the we can use the same design over a range of different
resolutions without having to calibrate the delay.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-03 15:07:17 +02:00
02b5ce82ad
imageon_loopback: Invert transmit clock
...
The ADV7511 samples on the rising edge. Update the data on the falling
edge, this gives us a larger margin and improved signal stability.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-03 15:07:17 +02:00
281cab091c
imageon_loopback: Create a clock for hdmi_rx_clock
...
Create a clock for the HDMI clock to make sure that the timing paths are
properly constraint.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-03 15:07:17 +02:00
95500d4022
fmcomms2_rfsom: Fix GPIO connections
2015-07-03 13:03:19 +03:00
eb3a0c179b
imageon: Put HDMI input/output FF into the IOB
...
This gives us predictable delays as well as very small skew between the induvidual data lines.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-02 18:33:32 +02:00
e269fe1dd0
Revert "imageon: Connect raw data to ILA"
...
This reverts commit 9e4fb2d048
2015-07-02 18:33:32 +02:00
18e8914087
fmcjesdadc1/a5gt: pn-errors version
2015-07-01 13:43:12 -04:00
Rejeesh Kutty
Istvan Csomortani
Adrian Costina
Lars-Peter Clausen