9043f3737b
Revert "a10gx: Optimise the base design"
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This reverts commit 9afc871b70
2020-08-11 10:14:18 +03:00
4af0c98c56
a10gx: Fix exceptionSlave interface definition for HPS
2020-08-11 10:14:18 +03:00
0b51c474a1
a10gx: Add a Avalon Pipeline Bridge between EMIF and DMA's
2020-08-11 10:14:18 +03:00
0de5039b96
avl_dacfifo: add_intance command must have a version attribute
2020-08-11 10:14:18 +03:00
359e5d94ec
a10gx: Remove constraint from eth_ref_clk
2020-08-11 10:14:18 +03:00
193fce338d
cn0540: Initial commit
2020-05-28 18:49:35 +03:00
ef15757d9e
common:vcu118: support for plddr4 adc and dac fifo
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Use 1GB from the DDR4 for either ADC or DAC sample buffering.
Max theoretical bandwidth of 19.2 GB/s
2020-03-03 15:49:11 +02:00
501abfd53a
common/coraz7s: Fixed ethernet issue
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fixed coraz7s preset; cleaned up lines which generated warnings
2020-02-18 13:24:43 +02:00
3c83694755
adi_fir_filter_bd.tcl: Synchronize the control GPIO input to the core clock
2019-12-03 17:27:56 +02:00
c2726ceac9
common:vcu118: move system memory to DDR C2
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The DDR controller for C2 for is much closer to the transceivers which
connect to the FMCp connector so designs does not have to span over all
three SLRs just over two reducing implementation and timing closure effort.
2019-11-28 16:17:44 +02:00
40d839df5f
coraz7s: Initial commit
2019-11-15 14:35:00 +02:00
23d29e7a15
a10soc_system_qsys: sys_dma_clk clock_source inherit its clock frequency from its source
2019-10-02 15:32:17 +03:00
bc2f916dfc
a10soc: Synchronize resets to the reset source
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Resets de-assertion should be synchronized to its associated clock.
2019-10-02 15:32:17 +03:00
b7d48b8c74
common/vcu118: Balance clocks
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Minimize skew on synchronous CDC timing paths between clocks originating
from the same MMCM source. (sys_mem_clk and sys_cpu_clk)
This is required mostly by the smart interconnect.
The CLOCK_DELAY_GROUP property must be applied directly to the output net of BUFGs.
2019-09-16 10:00:14 +03:00
36a1767329
Add generic fir filters processes for RF projects
2019-08-20 16:24:47 +03:00
0261eade0c
zynq:all: fix SPI clock constraint
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According to data sheets the EMIO SPI controller maximum frequency is
just 25MHz. Constrain the SPI clock accordingly.
2019-08-09 16:39:56 +03:00
0680e44330
system_id: deployed ip
2019-08-06 16:53:11 +03:00
4fe5f007cb
system_id: added axi_sysid ip core and tcl
2019-08-06 16:53:11 +03:00
6a721c0bf0
adi_env: Update system level environment variable definition
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Our internal repository was changed from phdl to ghdl. Update the
adi_env.tcl scripts and other scripts, which depends on the $ad_ghdl_dir
variable. This way the tools will see all the internal IPs too.
2019-07-22 11:00:45 +03:00
e1d9a36ae0
scripts/adi_project_intel: Rename ALT_NIOS_MMU_ENABLED to NIOS_MMU_ENABLED
2019-06-29 06:53:51 +03:00
79b6ba29ce
all: Rename altera to intel
2019-06-29 06:53:51 +03:00
019390f9bf
block_design: Updates with new reset net variables
2019-06-11 18:13:06 +03:00
de510b45ab
base: Add system_processor_rst for all the global clocks
2019-06-11 18:13:06 +03:00
20c714eccf
common: Define three global clock nets
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For all the Xilinx base design, define three global clock nets, which
are saved in the following three global variable: $sys_cpu_clk, $sys_dma_clk
and $sys_iodelay_clk.
These clock nets are connected to different clock sources depending of
the FPGA architecture used on the carrier. In general the following
frequencies are used:
- sys_cpu_clk - 100MHz
- sys_dma_clk - 200MHz or 250Mhz
- sys_iodelay_clk - 200MHz or 500Mhz
2019-06-11 18:13:06 +03:00
70b7d69ff8
whitespace: Delete all trailing white spaces
2019-06-07 10:20:15 +03:00
9afc871b70
a10gx: Optimise the base design
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Add a clock crossing bridge for the interfaces that runs on a different
clock than the emif_user_clk.
This way we can simplify the main interconnect, and prevent occasional
timing violations.
2019-06-04 11:28:37 +03:00
08d01789c8
microblaze: add SPI clock constraint
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The SPI clock is a generated clock from the system clock. Worst case
scenario is that the system clock is divided by two.
2019-05-30 14:55:11 +03:00
5986e87a1f
zynq/zynqmp: create a 50MHz clock on the SPI clock outputs of the PS
2019-05-30 14:55:11 +03:00
4fca24d41f
vc707: define 125 MHz SGMII clock
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Constrain the clock path to 125 MHz corresponding to the output of
ICS844021I which has a 25 MHz reference.
2019-05-30 14:55:11 +03:00
958ba7c3af
common zed, zc702 and zc706: Remove parameter assignment
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The SYNC_TRANSFER_START parameter is disabled in this configuration
of the axi_dmac, trying to set the parameter will generate a warning.
2019-05-27 16:48:26 +03:00
31e7c8e778
zc706/plddr3_adc|dacfifo_bd: PL DDR3 size is 1Gbyte
2019-05-06 17:17:00 +03:00
dc5f90098e
vcu118: Initial commit for common files
2019-04-17 14:24:35 +03:00
660f66af98
kcu105: Moved to smartconnect
2019-04-15 17:49:11 +03:00
bd79a0040e
common/vc707: Tools version update (2018.3)
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Use 200MHz clock for Ethernet subsystem ref_clk
2019-04-12 10:48:50 +03:00
bed5ce516c
adcfifo/dacfifo: fix alignments
2019-01-23 14:45:45 +02:00
a3766b464b
adcfifo/dacfifo: Use proc to create infrastructure
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Create the dacfifo/adcfifo infrastructure with procedures.
This will allow moving the parameters of the dac/adcfifo inside
the block design so it can be calculated based on other parameters.
2019-01-23 14:45:45 +02:00
70fe72da16
a10soc: Common, increase SPI frequency to 10MHz
2018-11-27 15:31:21 +02:00
52085c1739
a10soc: set "FORCE ALL USED TILES TO HIGH SPEED"
2018-11-27 15:31:21 +02:00
9c6da0ff45
zed, zc702, zc706, ccfmc: Send video trough axis interface
2018-09-27 11:45:28 +03:00
985f35225c
sys_gen: Remove deprecated script
2018-08-23 18:41:48 +03:00
4f1c748d8a
common/zc702: Replace VDMA with ADI DMAC
2018-08-20 14:28:01 +03:00
6ef268bb31
common/zc706: Replace VDMA with ADI DMAC
2018-08-20 14:28:01 +03:00
a0e3997687
common/zed_system_bd.tcl: Replace VDMA
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Replace Xilinx VDMA IP with ADI axi_dmac IP.
2018-08-20 14:28:01 +03:00
1c75c7b9ca
common/mitx045: Remove carrier support
2018-08-16 10:05:02 +03:00
ebae8bf8c1
Remove interrupts from system_top for all xilinx projects
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- remove interrupts from system_top
- for all suported carriers:
- remove all interrupt bd pins
- connect to GND all initial unconnected interrupt pins
- update ad_cpu_interrupt procedure to disconnect a interrupt from GND
before connectiong it to another pin.
2018-08-10 10:10:58 +03:00
74288cf9cb
axi_hdmi_tx: Added INTERFACE parameter for selecting the interface type
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Update all carriers/projects bd for configurable video interface:
- common zc702, zc706, zed
- adrv9361z7035/ccfmc_lvds
- imageon
2018-07-24 15:56:22 +03:00
bcba21da71
zcu102: updated IOSTANDARD of Bank 44 IOs to match VCCO 3.3V
2018-06-05 08:52:50 +01:00
8a2a394790
Remove unused projects/common/Makefile
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This file only references a subdirect that no longer exists, but nothing
else.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-04-11 15:09:54 +03:00
8e042193be
DE10: Initial commit
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These modifications were taken from the old dev branch.
2018-04-11 15:09:54 +03:00
72431ff952
a10soc: Connect AXI register reset
2018-04-11 15:09:54 +03:00
Istvan Csomortani
Stanca Pop
Laszlo Nagy
Arpadi
AndreiGrozav
Adrian Costina
Lars-Peter Clausen
Rejeesh Kutty