Istvan Csomortani
|
5fe008d887
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axi_ad9371: Update dac_clk_ratio to 2
DAC sampling frequency is two times of the JESD204
core clock.
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2017-05-10 11:12:45 +03:00 |
|
Istvan Csomortani
|
1c23cf4621
|
all: Update verilog files to verilog-2001
|
2017-04-13 11:59:55 +03:00 |
AndreiGrozav
|
a505d304af
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Add up_dac_common missing connections
|
2016-10-12 13:20:26 +03:00 |
|
Istvan Csomortani
|
913eafed48
|
up_drp : Update the DRP interface to support Altera platforms
|
2016-09-21 15:00:45 +03:00 |
Rejeesh Kutty
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b5b05bb9d1
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axi_ad9371: added
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2016-05-20 11:41:54 -04:00 |