Commit Graph

5714 Commits (d9639db991aaa38c111dd0262554a28d83ecd15b)

Author SHA1 Message Date
Istvan Csomortani d9639db991 m2k: Use adi_project_create instead of adi_project 2021-01-15 15:26:43 +02:00
Istvan Csomortani e41ba7f6f5 adrv9009zu11eg: Use adi_project_create instead of adi_project 2021-01-15 15:26:43 +02:00
Istvan Csomortani 9ec3408c79 adi_project_xilinx: Fix the adi_project process
In most of the standalone projects the generic project creation flow is not followed. The project's device
is defined manualy. This fix makes sure that those projects still builds without an issue.

NOTE: In these case we should use adi_project_create directly in system_project.tcl.
2021-01-15 15:26:43 +02:00
Sergiu Arpadi b9ac8df503 project-xilinx.mk: Add *.hbs to clean list 2021-01-15 13:50:53 +02:00
Sergiu Arpadi 067b57d404 vc707: Fix mdio intf 2021-01-15 13:50:53 +02:00
Sergiu Arpadi c54552d823 adi_project_xilinx: Add env var
add ADI_DISABLE_MESSAGE_SUPPRESION which disables
adi_xilinx_msg.tcl

projects/scripts/adi_project_xilinx.tcl
2021-01-15 13:50:53 +02:00
Sergiu Arpadi e252d538c2 adi_ip_xilinx: Add env var
add ADI_DISABLE_MESSAGE_SUPPRESION which
disables adi_xilinx_msg.tcl
2021-01-15 13:50:53 +02:00
Sergiu Arpadi ead4513ad6 adi_xilinx_msg: Downgrade Synth 8-2490 2021-01-15 13:50:53 +02:00
Arpadi 51b5e4f58b tcl: Change Vivado version to 2020.1
handoff is now exported as .xsa
2021-01-15 13:50:53 +02:00
Adrian Costina fbb2a0e1a0 de10nano: Add hps_conv_usb_n signal to stabilize UART lines
Without defining this signal, the UART lines receive garbage data
when no cable is connected to the J4 USB UART port.
The GPIO9 is enabled in the reference base design along with the
4MA CURRENT_STRENGTH constraint on the UART pins
2021-01-13 15:36:45 +02:00
Istvan Csomortani dee108ba22 fmcomms8/intel: Fix fPLL configuration
When phase alignment is active, the PFD frequency value should be used
as outclk1 actual frequency.

The configuration interface of the fPLL does not support fractional values.
If the reference clock is fractional, the tool will throw an error that requirement
above is not respected.

Round up the reference clock for the SERDES and the lane rate in order to
overcome this issue, until it's not fixed by Intel.
2021-01-12 19:34:44 +02:00
Istvan Csomortani 85f5dc8230 ad9371x/intel: Fix fPLL configuration
When phase alignment is active, the PFD frequency value should be used
as outclk1 actual frequency.

The configuration interface of the fPLL does not support fractional values.
If the reference clock is fractional, the tool will throw an error that requirement
above is not respected.

Round up the reference clock for the SERDES and the lane rate in order to
overcome this issue, until it's not fixed by Intel.
2021-01-12 19:34:44 +02:00
Istvan Csomortani d539a8119c adrv9009/intel: Fix fPLL configuration
When phase alignment is active, the PFD frequency value should be used
as outclk1 actual frequency.

The configuration interface of the fPLL does not support fractional values.
If the reference clock is fractional, the tool will throw an error that requirement
above is not respected.

Round up the reference clock for the SERDES and the lane rate in order to
overcome this issue, until it's not fixed by Intel.
2021-01-12 19:34:44 +02:00
Istvan Csomortani b8d294cdd9 intel/jesd204: clock_source instance version is 19.3 2021-01-12 19:34:44 +02:00
aholtzma bab3426f91 scripts: allow directly specifying a device when creating a project
Add a layer under adi_project that allows you to directly specify a device/board combination without determining it from the project name.
2021-01-12 14:13:07 +02:00
Laszlo Nagy 14307856ea xilinx:adxcvr: PRBS support
The new REG_PRBS_CNTRL and REG_PRBS_STATUS registers expose controls of internal
PRBS generators and checkers allowing the testing the multi-gigabit serial link
at the physical layer without the need of the link layer bringup.
2021-01-12 13:40:42 +02:00
Istvan Csomortani b989ba36d1 axi_spi_engine: Fix util_axis_fifo instance related issues 2021-01-08 12:29:26 +02:00
sergiu arpadi 5c87e5b1a7 cn0501: Initial commit for Coraz7s 2020-12-18 14:05:56 +02:00
Sergiu Arpadi 71009e74ff ad7768_if: Remove buffers, add parallel data path 2020-12-15 15:16:14 +02:00
Lars-Peter Clausen c6c45fe1d5 adi_jesd204: Configure fPLL phase aligned mode
In phase aligned mode the fPLL uses an external feedback path to better
align the phase of the PLL output to the phase of the external reference
clock.

This mode is required for deterministic latency to be able to sample SYSREF
which is source synchronous to the external reference clock signal.

So far phase aligned mode had been disabled since manual PLL calibration
would fail in this mode under certain (unknown) circumstances and dynamic
reconfiguration of the PLL would not work.

The latest Intel Arria 10 transceiver datasheet contains instructions for
the proper calibration sequence to make it work when the PLL is configured
for phase aligned mode. Software has been updated accordingly, so enable
phase aligned mode.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2020-12-14 13:59:11 +02:00
AndreiGrozav c0de649e2e axi_hdmi_tx: Remove deprecated constraint 2020-12-08 14:38:04 +02:00
AndreiGrozav fa67eb5532 adv7513_de10nano: Fix gpio_bd assignments 2020-12-08 14:38:04 +02:00
AndreiGrozav e331abedc6 common/de10nano: Cosmetic updates only 2020-12-08 14:38:04 +02:00
AndreiGrozav 8d378c56bf common/de10nano: Full HD 60 FPS support
-change the video memory interfacing from f2h_axi_slave to
f2h_sdram0
- add f2h_sdram1 port as the default interface for converter DMA
- set as default the full HD resolution at 60 FPS (pixel clock 148.5MHz)
- use a second 200MHz(198MHz) clock from the pixel_clk_pll, as DMA source
to destination clock.
2020-12-08 14:38:04 +02:00
Istvan Csomortani f7b8a2dfb5 axi_dmac: Update IP with the new util_axis_fifo
Update instantiation, false path definitions and make file.
2020-12-04 11:00:53 +02:00
Istvan Csomortani eb7e533d66 spi_engine: Update util_axis_fifo instances 2020-12-04 11:00:53 +02:00
Istvan Csomortani 5ac728392d util_axis_fifo: Refactoring
Refactor the AXI4 stream FIFO implementation.

  - Define a single address generator which supports both single and double
clock mode. (synchronous and asynchronous)
  - Fix FIFO status bits (empty/full). NOTE: In asynchronous mode the
flags can have a several clock cycle delay in function of the upstream/downstream
clock ratio.
  - In synchronous none FIFO mode (ADDRESS_WIDTH==0), the module acts as
    an AXI4 stream pipeline.
2020-12-04 11:00:53 +02:00
Laszlo Nagy 5df2961624 ad_mux: another fix cases where channel number is not power of mux size 2020-11-27 09:45:11 +02:00
Laszlo Nagy 0badfdfa31 ad_mux: fix cases where channel number is not power of mux size 2020-11-27 09:45:11 +02:00
Laszlo Nagy 3dd370a27c ad9081_fmca_ebz: enable xbar in DAC TPL 2020-11-27 09:45:11 +02:00
Laszlo Nagy 01f4576fcd ad_ip_jesd204_tpl_dac: added xbar for user channels (dma data)
Allow channels received from dma to re-map to other channels, e.g. allowing
broadcasting the same channel to all channels.

The feature is selectable with synthesis parameter and disabled by default.
2020-11-27 09:45:11 +02:00
Laszlo Nagy 5c561665b0 common/ad_mux: Pipelined mux, rtl and TB
Build a large mux from smaller ones defined by the REQ_MUX_SZ parameter
 Use EN_REG to add a register at the output of the small muxes to help
 timing closure.
2020-11-27 09:45:11 +02:00
Laszlo Nagy 1c71815bd7 up_dac_channel: add register for dma data xbar
This commit adds two fields:
1. source channel selection -  Sets the channel number the for the source data.
2. DMA enable mask - When this bit is set do not drive the enable line
   towards the DMA interface.
2020-11-27 09:45:11 +02:00
Laszlo Nagy ad755788a0 ad9081_fmca_ebz/zc706: Initial version
M=8 L=4 SampleRate=250 MSPS
LaneRate=10 Gbps
2020-11-12 15:46:27 +02:00
Laszlo Nagy e9f319e3d7 ad9081_fmca_ebz: HP0 is already initialized in ZC706
On carriers like ZC706 the HP0 interconnect is in already in use so it must
not be initialized here.
2020-11-12 15:46:27 +02:00
Adrian Costina b080b52a14 daq3:zcu102: Connect overflow pins for the AD9680 TPL 2020-11-11 14:24:02 +02:00
Istvan Csomortani 2799777657 adrv9009zu11eg/adrv2crr_fmc: Fix hmc7044_car_gpio connections 2020-11-11 07:07:29 -05:00
Adrian Costina ecd880d44c adrv9009zu11eg:fmcomms8: Fix SPI timing constraint 2020-11-05 17:42:41 +02:00
Adrian Costina 7309da59d1 ad_ip_jesd204_tpl_dac: Switch to sync arm toggling instead of setting only
Added the second flip flop for timing reasons
2020-11-05 17:42:41 +02:00
Adrian Costina c3465789b8 up_dac_common: Move the sync status to register 0x1a to mirror adc path 2020-11-05 17:42:41 +02:00
stefan.raus 685ca91f19 ad_fmclidar1_ebz/a10soc: Fix a typo
Fixing a typo in projects/ad_fmclidar1_ebz/a10soc/system_top.v.
2020-11-05 12:53:50 +02:00
aholtzma 2ff5420630 Update system_top.v
Add a comment that the spi CS decoding is tied to a setting in the device tree.
2020-11-02 16:59:08 +02:00
IMoldovan 78b2ae02a1 ad9434_fmc,ad9467_fmc,fmcadc5: Update projects to use ad_iobuf, not IOBUF 2020-11-02 16:13:35 +02:00
Adrian Costina a3a610728c intel: Update projects to use ad_iobuf instead of ALT_IOBUF 2020-11-02 16:13:35 +02:00
Adrian Costina ae7ec82334 adrv9009zu11eg: Update spi module to use generic verilog 2020-11-02 16:13:35 +02:00
Adrian Costina 9093a8c428 library: Move ad_iobuf to the common library, as it's not Xilinx specific
Updated all system_project and Makefiles
2020-11-02 16:13:35 +02:00
AndreiGrozav 912e09ad18 m2k: Add DAC last sample connections 2020-11-02 15:50:12 +02:00
AndreiGrozav 0ddb08070a axi_ad9963: Add last sample hold support
The mechanism is controlled by axi_dac_interpolate.
2020-11-02 15:50:12 +02:00
AndreiGrozav 4f4a4208cd axi_dac_interpolate: Add last sample support
This feature will allow the user to hold(indefinitely) the last sample, from an
ongoing DMA transfer, simple or cyclic(stooped by user or trigger).

This commit also adds as functionality option:
-synchronized stop between the two channels(DMAs)
-stop by trigger
2020-11-02 15:50:12 +02:00
Istvan Csomortani d676cfd64f adv7513/de10nano: Define the USB clock 2020-10-30 10:55:01 +02:00