9ec3408c79
adi_project_xilinx: Fix the adi_project process
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In most of the standalone projects the generic project creation flow is not followed. The project's device
is defined manualy. This fix makes sure that those projects still builds without an issue.
NOTE: In these case we should use adi_project_create directly in system_project.tcl.
2021-01-15 15:26:43 +02:00
b9ac8df503
project-xilinx.mk: Add *.hbs to clean list
2021-01-15 13:50:53 +02:00
c54552d823
adi_project_xilinx: Add env var
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add ADI_DISABLE_MESSAGE_SUPPRESION which disables
adi_xilinx_msg.tcl
projects/scripts/adi_project_xilinx.tcl
2021-01-15 13:50:53 +02:00
ead4513ad6
adi_xilinx_msg: Downgrade Synth 8-2490
2021-01-15 13:50:53 +02:00
51b5e4f58b
tcl: Change Vivado version to 2020.1
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handoff is now exported as .xsa
2021-01-15 13:50:53 +02:00
bab3426f91
scripts: allow directly specifying a device when creating a project
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Add a layer under adi_project that allows you to directly specify a device/board combination without determining it from the project name.
2021-01-12 14:13:07 +02:00
d6b23d5149
scripts/adi_pd_intel: Delete noisy print outs
2020-10-17 08:02:33 +03:00
c656a2e29b
sysid: Initialize parameter
2020-09-30 19:12:24 +03:00
5644907f75
adi_intel_msg: Dissable "unused TX/RX channel" critical warning for Stratix 10
2020-09-25 12:56:14 +03:00
f2f6422751
sysid: Fix board/project name underscore issue
2020-09-17 10:32:58 +03:00
6cea8ce777
adi_project_intel: Add de10nano support
2020-09-15 18:14:23 +03:00
f57643b451
sysid_intel: Added adi_pd_intel.tcl
2020-09-11 15:46:06 +03:00
2b5136db98
scripts/project_intel.mk: Update CLEAN targets
2020-09-09 14:15:37 +03:00
f9c4283f45
stratix10soc: Initial commit of base design
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Note: Currently we have a engineering sample version 2 board.
2020-09-09 14:15:37 +03:00
eb2f211d30
scripts/intel: Add message severity definition file
2020-08-25 14:46:52 +03:00
fa0b39fa20
adi_project_intel: Update QSYS generation
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In Quartus Prime in place of the set_domain_assignment command, the
set_interconnect_requirement command is used.
2020-08-17 12:02:49 +03:00
f3b69c15c9
scripts/intel: Update version check
2020-08-12 10:33:29 +03:00
218f45a0df
scripts/intel: Set supported Quartus version to 19.3
2020-08-12 10:33:29 +03:00
5ba3448987
scripts/project-intel: Update CLEAN target
2020-08-11 10:14:18 +03:00
8fd1ad64d6
quartus: Increase tool version to 19.2
2020-08-11 10:14:18 +03:00
f3142a6a7a
adi_project_intel: set_interconnect_requirment command is deprecated
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Use set_domain_assignment to set up the maximum pipeline stages for the
main interconnect.
2020-08-11 10:14:18 +03:00
967a138d0f
adi_project_intel: Add support for Quartus Pro
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By defualt the supported tool chain is Quartus PRO. If you want to
build the project with Quartus Standard, you need to define an environment
variable called QUARTUS_PRO_ISUSED with the value 0. (e.g. export
QUARTUS_PRO_ISUSED=0 )
Note: Not all projects going to build on Quartus Standard, you should
fix the errors if there is any.
2020-08-11 10:14:18 +03:00
054193e083
adi_project_intel: Delete all MESSAGE_DISABLE assignment
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These kind of assignments should be placed into file like
~/projects/scripts/adi_xilinx_msg.tcl
2020-08-11 10:14:18 +03:00
4ca1311d57
quartus_pro: Global assignment ENABLE_ADVANCED_IO_TIMING is not supported
2020-08-11 10:14:18 +03:00
9c8190f709
adi_project_xilinx.tcl: discover all timing failures
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Look for an overall indicator of timing failure.
Create critical warning if timing is failed.
2020-05-26 14:47:38 +03:00
db6af63583
scripts/adi_env.tcl: print in logs system variables are used
2020-05-20 19:07:23 +03:00
6535e5b2ba
scripts/xilinx: Version mismatch is upgraded to ERROR
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There is a major compatibility issue between 2019.1 and 2019.2.
The file system_top.hdf got a different file extention. This will
cause a compilation failer in the end of the build. To save time
and fail earlier, upgrade the version mismatch message to ERROR.
If user still wants to build a branch with different tool version
the variable ADI_IGNORE_VERSION_CHECK should be set to 1.
2020-05-15 12:16:35 +03:00
1f7671cb36
scripts/adi_env.tcl: helper function for environment variables
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Ease the access of the environment variables.
2020-03-10 18:19:03 +02:00
3192807f22
adi_project_xilinx: Fixed variable name
2020-02-14 11:22:46 +02:00
c5e03eb196
adi_project_xilinx: Added power analysis procedure
2020-02-14 11:22:46 +02:00
78a1e54a33
adi_project_xilinx.tcl: Generate resource utilization for IPs
2020-02-13 11:33:02 +02:00
135538b521
adi_project: Fixed kcu105 board file selection
2020-01-16 17:16:58 +02:00
e773b22087
adi_project: Updated board files version selection
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vivado will automatically select the latest version for a given board
2020-01-14 17:16:01 +02:00
d86fbb2a08
adi_board: fixed ddr memory mapping for microblaze projects
2020-01-13 12:25:23 +02:00
34ea5efdff
adi_project_xilinx: Use the latest board files
2020-01-13 12:25:23 +02:00
adfeb435a4
scripts: Update Vivado version to 2019.1
2020-01-13 12:25:23 +02:00
82021edffe
adi_board.tcl:ad_xcvrcon: do not reorder common control
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When channels are not swapped in groups of four but are completely out of order
the common control channel can't be reordered based on the index of the
channel.
2019-11-30 12:29:32 +02:00
8c39cf8560
scripts: adi_board.tcl: Update the axi_adxcvr to util_adxcvr connections
2019-11-26 12:57:53 +02:00
40d839df5f
coraz7s: Initial commit
2019-11-15 14:35:00 +02:00
fd4d32c408
projects/scripts/*xilinx*: Generate report utilization extra files
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Add commands to generate one extra file with resource utilization, in CSV format.
New commands executes only if ADI_GENERATE_UTILIZATION env variable is set.
2019-10-18 13:42:34 +03:00
af94487f57
adi_project_intel: Enable HPS internal timing
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It's recommended to use this global assignment so the tool can make a
more in-depth timing analysis.
2019-10-02 15:32:17 +03:00
75d263afc5
adi_project_xilinx: Add constraint files to constr_1 file set
2019-09-27 18:21:25 +03:00
b174333fa2
project-xilinx.mk: Clean generated file by sysid
2019-09-27 13:16:19 +03:00
442b38033a
sys_id: added catch to git status check
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made error checking more general
2019-09-26 16:26:02 +03:00
5e08e2d548
project-xilinx.mk: Fix build condition
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"prepare_incremental_compile" is defined as a phony target, but is also a
prerequisite of a real target. This will lead to a complete project build
every time make is called.
To fix the issue the functionality of prepare_incremental_compile target
was included in the generic project build target.
2019-09-12 13:23:09 +03:00
36a1767329
Add generic fir filters processes for RF projects
2019-08-20 16:24:47 +03:00
4fe5f007cb
system_id: added axi_sysid ip core and tcl
2019-08-06 16:53:11 +03:00
14a4acfd0e
projects/scripts: Fix a typo in adi_env.tcl
2019-07-25 17:58:36 +03:00
fa610d36c6
ad_ghdl_dir: Fix global variable name
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In #PR318 the global variable $ad_phdl_dir name were changed to
$ad_ghdl_dir.
2019-07-23 10:29:37 +01:00
6a721c0bf0
adi_env: Update system level environment variable definition
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Our internal repository was changed from phdl to ghdl. Update the
adi_env.tcl scripts and other scripts, which depends on the $ad_ghdl_dir
variable. This way the tools will see all the internal IPs too.
2019-07-22 11:00:45 +03:00
Istvan Csomortani
Sergiu Arpadi
aholtzma
Stanca Pop
Laszlo Nagy
sraus
Adrian Costina
AndreiGrozav
István Csomortáni