Commit Graph

2620 Commits (da50d682c5dbf2210e08d4e39dc3f44aca04bf33)

Author SHA1 Message Date
Lars-Peter Clausen da50d682c5 ad6766evb: Use new pack infrastructure
Use the new util_cpack2 and util_upack2 cores. They have lower utilization
that the old util_cpack and util_upack cores.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-11-28 11:33:11 +02:00
Lars-Peter Clausen 9b919636ca fmcjesdadc1: Use new pack infrastructure
Use the new util_cpack2 and util_upack2 cores. They have lower utilization
that the old util_cpack and util_upack cores.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-11-28 11:33:11 +02:00
Lars-Peter Clausen 1d223c19f8 fmcadc4: Use new pack infrastructure
Use the new util_cpack2 and util_upack2 cores. They have lower utilization
that the old util_cpack and util_upack cores.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-11-28 11:33:11 +02:00
Lars-Peter Clausen 1375dcfeaa daq3: Use new pack/unpack infrastructure
Use the new util_cpack2 and util_upack2 cores. They have lower utilization
that the old util_cpack and util_upack cores.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-11-28 11:33:11 +02:00
Lars-Peter Clausen b9958cac00 daq2: Use new pack/unpack infrastructure
Use the new util_cpack2 and util_upack2 cores. They have lower utilization
that the old util_cpack and util_upack cores.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-11-28 11:33:11 +02:00
Lars-Peter Clausen 76f6428bfc usrpe31x: Use new pack/unpack infrastructure
Use the new util_cpack2 and util_upack2 cores. They have lower utilization
that the old util_cpack and util_upack cores.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-11-28 11:33:11 +02:00
Lars-Peter Clausen aed8478d10 adrv9371x: Use new pack/unpack infrastructure
Use the new util_cpack2 and util_upack2 cores. They have lower utilization
that the old util_cpack and util_upack cores.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-11-28 11:33:11 +02:00
Lars-Peter Clausen 2462f8e50f adrv9009: Use new pack/unpack infrastructure
Use the new util_cpack2 and util_upack2 cores. They have lower utilization
that the old util_cpack and util_upack cores.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-11-28 11:33:11 +02:00
Matt Fornero 3052c28c01 adrv9364: Use new pack/unpack infrastructure
Use the new util_cpack2 and util_upack2 cores. They have lower utilization
that the old util_cpack and util_upack cores.

Signed-off-by: Matt Fornero <matt.fornero@mathworks.com>
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-11-28 11:33:11 +02:00
Matt Fornero 0a67746352 adrv9361: Use new pack/unpack infrastructure
Use the new util_cpack2 and util_upack2 cores. They have lower utilization
that the old util_cpack and util_upack cores.

Signed-off-by: Matt Fornero <matt.fornero@mathworks.com>
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-11-28 11:33:11 +02:00
Lars-Peter Clausen f79039b4d4 fmcomms5: Use new pack/unpack infrastructure
Use the new util_cpack2 and util_upack2 cores. They have lower utilization
that the old util_cpack and util_upack cores.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-11-28 11:33:11 +02:00
Lars-Peter Clausen 27c3231c1b arradio: Use new pack/unpack infrastructure
Use the new util_cpack2 and util_upack2 cores. They have lower utilization
that the old util_cpack and util_upack cores.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-11-28 11:33:11 +02:00
Lars-Peter Clausen 078a7fffc8 fmcomms2: Use new pack/unpack infrastructure
Use the new util_cpack2 and util_upack2 cores. They have lower utilization
that the old util_cpack and util_upack cores.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-11-28 11:33:11 +02:00
Adrian Costina 401395cdd1 adrv9009: A10GX: Initial commit 2018-11-27 15:31:21 +02:00
Adrian Costina 70fe72da16 a10soc: Common, increase SPI frequency to 10MHz 2018-11-27 15:31:21 +02:00
Adrian Costina e4048c7b04 adrv9009: A10SOC: Add second observation channel 2018-11-27 15:31:21 +02:00
Adrian Costina 52085c1739 a10soc: set "FORCE ALL USED TILES TO HIGH SPEED" 2018-11-27 15:31:21 +02:00
Adrian Costina f12bd3d246 adrv9009: A10SOC: Initial commit 2018-11-27 15:31:21 +02:00
Istvan Csomortani 559e00fd75 adrv9009/zcu102: Increase DAC buffer depth to 18Mb 2018-10-11 16:57:30 +03:00
Istvan Csomortani 10deddd6d2 adrv9371/zcu102: Tune the differential swing of the TX lines 2018-10-04 14:37:02 +03:00
Istvan Csomortani cff8341c18 daq3/zcu102: Add custom configuration for CPLL
To support 12.33 Gbps add a custom configuration for the CPLLs.
2018-10-04 14:37:02 +03:00
Istvan Csomortani 1931d65b7a adrv9009/zcu102: Update initial configuration for GT clock output control 2018-10-04 14:37:02 +03:00
Laszlo Nagy 4ce153e6e1 all/system_top.v: loopback gpio lines
Create loopback on unused GPIO lines since Linux may rely on it.
2018-10-04 14:19:37 +03:00
Istvan Csomortani 2b868c2857 adi_project.tcl: Update the ZCU102 board preset version 2018-10-03 15:54:29 +03:00
Istvan Csomortani bbb72d2c7e fmcomms2/zc702: Modify implementation strategy to Performance Exlpore
When we improve timing by modifying the implementation strategies,
the general rule of thumb is "less is always more".

Timing did not fail in synthesis, so we leaving the synthesis
strategy in default.
After several parallel runs with various strategies, the
"Performance_Explore" strategy gave the best result for
implementation.
2018-09-27 11:46:12 +03:00
AndreiGrozav b0b149244b daq2_kcu105: Change implementation strategy
Use Performance_Retiming strategy to meet timing.
2018-09-27 11:45:52 +03:00
AndreiGrozav 9c6da0ff45 zed, zc702, zc706, ccfmc: Send video trough axis interface 2018-09-27 11:45:28 +03:00
Lars-Peter Clausen 97409dcb88 adi_board.tcl: ad_xcvrcon: Fix width of sync port for multi-link setups
Each individual link of a multi-link has its own sync signal. The top level
sync port that is created by the ad_xcvrcon function is always a single bit
single though.

This results in only the sync signal of the first link being routed while
others are ignored.

To fix this make sure that for multi-link setups the sync port is a vector
port with the width equal to the number of links.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-09-10 13:46:38 +02:00
Adrian Costina 0e8515a90b fmcomms2:kcu105: Performance_ExploreWithRemap fixes DDR timing violation 2018-09-05 15:53:36 +03:00
Adrian Costina 240b75cc45 fmcadc2: VC707, specifically connect spi_csn[2:0] to the fmcadc2_spi module 2018-09-05 15:53:18 +03:00
Adrian Costina f4cc89a7f3 fmcomms2: cleanup system_top for kc705,kcu105, vc707 and zcu102 2018-09-05 15:53:02 +03:00
Adrian Costina 2f4904e4d2 motcon2_fmc: Remove muxaddr_out, refclk and refclk_rst from system_bd
- refclk and refclk_rst were used for ethernet IDELAY, but are not needed anymore
- muxaddr_out pins overlap with regular GPIOs in the Zed base design. The XADC mux GPIOs can be controlled through that. Cusomters that want to directly control the pins through XADC IP must modify the design
2018-09-05 15:12:51 +03:00
Istvan Csomortani a387018f7a daq3:kcu105: Performance_ExploreWithRemap results the highest WNS 2018-08-23 18:41:48 +03:00
Istvan Csomortani 15863795e8 adrv9371x:kcu105: Performance_Retiming results the highest WNS
In default strategy we having a few path with small negative slack inside of
the MIG, due to the high UI clock (300MHz).

This new strategy solves this issue.
2018-08-23 18:41:48 +03:00
Adrian Costina 86748825d0 m2k: Downgrade SPI related critical warning, as we use lower clock speed for power reasons 2018-08-23 18:41:48 +03:00
Istvan Csomortani 985f35225c sys_gen: Remove deprecated script 2018-08-23 18:41:48 +03:00
Istvan Csomortani 302ec5d68a adi_project_alt: Update Quartus version to 18.0.0 2018-08-23 18:41:48 +03:00
Istvan Csomortani b748488377 adi_board/adi_ip: Update Vivado version to 2018.2 2018-08-23 18:41:48 +03:00
Adrian Costina db51fb2829 daq3: ZCU102: Remove Offload FIFO for ADC path.
DAC FIFO cannot be increased because of timing violations
2018-08-23 18:06:32 +03:00
Adrian Costina 563710e904 daq3: ZCU102: Fixed system_top to be similar with ZC706. Updated constraints to specify exactly transceiver pin locations 2018-08-23 18:06:32 +03:00
AndreiGrozav 9418fcec24 fmcomms5/zcu102/system_constr.xdc: Fix typo 2018-08-23 18:01:20 +03:00
AndreiGrozav 97b1d3a21e common/daq2: Fix typo 2018-08-23 15:13:58 +03:00
AndreiGrozav 87b099d498 daq2/common: Add default util_adxcvr parameters 2018-08-21 17:12:31 +03:00
Istvan Csomortani 2293374307 adc|dac_fifo: Maximize the depth of each instance of the internal RAM FIFOs
The affected projects are:
  - FMCADC2/VC707 - 16Mb
  - FMCADC5/VC707 - 16Mb
  - DAQ2/ZC706  - ADC@1GB and DAC@8Mb
  - DAQ2/KC705  - ADC@4Mb and DAC@4Mb
  - DAQ2/VC707  - ADC@8Mb and DAC@8Mb
  - DAQ2/KCU105 - ADC@4Mb and DAC@4Mb
  - DAQ2/ZCU102 - ADC@8Mb and DAC@8Mb
  - DAQ3/ZC706  - ADC@1GB and DAC@8Mb
  - DAQ3/KCU105 - ADC@4Mb and DAC@4Mb
  - DAQ3/ZCU102 - ADC@8Mb and DAC@8Mb
  - ADRV9371x/KCU105 - DAC@8Mb
  - ADRV9371x/ZCU102 - DAC@16Mb
2018-08-21 11:44:05 +03:00
AndreiGrozav fa6f45a406 adrv936x, fmcomms2/5, usrpe31x: Fix warning on the dac path
Fix warnining regarding SYNC_TRANSFER_START parameter which doesn't
apply when the axi_dmac is configured for the tx path.
2018-08-20 14:29:57 +03:00
AndreiGrozav ec400e5865 adrv9361z7035/ccfmc: Replace VDMA with ADI DMAC 2018-08-20 14:28:01 +03:00
AndreiGrozav 4f1c748d8a common/zc702: Replace VDMA with ADI DMAC 2018-08-20 14:28:01 +03:00
AndreiGrozav 6ef268bb31 common/zc706: Replace VDMA with ADI DMAC 2018-08-20 14:28:01 +03:00
AndreiGrozav a0e3997687 common/zed_system_bd.tcl: Replace VDMA
Replace Xilinx VDMA IP with ADI axi_dmac IP.
2018-08-20 14:28:01 +03:00
AndreiGrozav 1c75c7b9ca common/mitx045: Remove carrier support 2018-08-16 10:05:02 +03:00