Add clock rate constraints for the eth1 rx clock, otherwise the tools
assume the RX paths are unconstrained and creates a bitstream which
violates hold times which causes bit errors on the RX path.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
This core has been superseded by the SPI Engine framework in combination
with the axi_generic_adc core.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The util_sigma_delta_spi peripheral can be used to seperate the interleaved
SPI bus and DRDY signals for a ADC from the Analog Devices SigmaDelta
family.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
SPI Engine is a highly flexible and powerful SPI controller framework. It
consist out of multiple sub-modules which communicate over well defined
interfaces. This allows a high degree of flexibility and re-usability while
at the same time staying highly customizable and easily extensible.
Currently included are four components:
* SPI Engine execution module: The excution module is responsible for
handling the low-level physical interface SPI logic.
* SPI Engine AXI interface module: The AXI interface module allows
memory mapped acccess to a SPI bus control stream and can be used to
implement a software driver that controls the SPI bus.
* SPI Engine offload module: The offload module allows to store a
predefined SPI Engine command and data stream which will be send out
when a external trigger signal is asserted.
* SPI Engine interconnect module: The interconnect module allows to
combine multiple control streams into a single stream giving multiple
control modules access to a execution module.
For more information see: http://wiki.analog.com/resources/fpga/peripherals/spi_engine
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Rejeesh Kutty
Istvan Csomortani
Lars-Peter Clausen
Adrian Costina