Commit Graph

155 Commits (dcdcbc9378b39fa1e2ece263f26f287f20857de5)

Author SHA1 Message Date
AndreiGrozav d894c30c2d Remove deprecated/unused parameters
adrv9009
adrv9371x
arradio
daq2
daq3
fmcomms2
fmcomms5
2019-03-30 11:26:11 +02:00
Laszlo Nagy b98eb28dca adrv9371: update adcfifo/dacfifo 2019-01-23 14:45:45 +02:00
Laszlo Nagy e864786d3a adrv9371: use generic TPL
Use the generic TPLs for a better scalability to ease lane number
reductions.
2019-01-14 17:21:00 +02:00
Lars-Peter Clausen aed8478d10 adrv9371x: Use new pack/unpack infrastructure
Use the new util_cpack2 and util_upack2 cores. They have lower utilization
that the old util_cpack and util_upack cores.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-11-28 11:33:11 +02:00
Istvan Csomortani 10deddd6d2 adrv9371/zcu102: Tune the differential swing of the TX lines 2018-10-04 14:37:02 +03:00
Laszlo Nagy 4ce153e6e1 all/system_top.v: loopback gpio lines
Create loopback on unused GPIO lines since Linux may rely on it.
2018-10-04 14:19:37 +03:00
Istvan Csomortani 15863795e8 adrv9371x:kcu105: Performance_Retiming results the highest WNS
In default strategy we having a few path with small negative slack inside of
the MIG, due to the high UI clock (300MHz).

This new strategy solves this issue.
2018-08-23 18:41:48 +03:00
Istvan Csomortani 2293374307 adc|dac_fifo: Maximize the depth of each instance of the internal RAM FIFOs
The affected projects are:
  - FMCADC2/VC707 - 16Mb
  - FMCADC5/VC707 - 16Mb
  - DAQ2/ZC706  - ADC@1GB and DAC@8Mb
  - DAQ2/KC705  - ADC@4Mb and DAC@4Mb
  - DAQ2/VC707  - ADC@8Mb and DAC@8Mb
  - DAQ2/KCU105 - ADC@4Mb and DAC@4Mb
  - DAQ2/ZCU102 - ADC@8Mb and DAC@8Mb
  - DAQ3/ZC706  - ADC@1GB and DAC@8Mb
  - DAQ3/KCU105 - ADC@4Mb and DAC@4Mb
  - DAQ3/ZCU102 - ADC@8Mb and DAC@8Mb
  - ADRV9371x/KCU105 - DAC@8Mb
  - ADRV9371x/ZCU102 - DAC@16Mb
2018-08-21 11:44:05 +03:00
Laszlo Nagy 31318cf311 all/system_top.v: drive unused gpio inputs with zero
The loopback on the unused gpio inputs consumes routing resources
while does not gives any value for the software.

Connect these lines to zero instead.
2018-08-10 17:00:11 +03:00
Laszlo Nagy 05789e8978 adrv9009/adrv9371x/fmcomms2:Drop usage of ad_iobuf on non-bidirectional IOs
Some projects use the ad_iobuf on IOs that are not bidirectional
producing synthesis warnings.

The change fixes warnings like:
[Synth 8-6104] Input port 'gpio_bd_i' has an internal driver
[Synth 8-6104] Input port 'gpio_status' has an internal driver
2018-08-10 17:00:11 +03:00
Laszlo Nagy fa7c85a9eb all: Drive undriven input signals, complete interface
- connect unused GPIO inputs to loopback
- connect unconnected inputs to zero
- complete interface for system_wrapper instantiated in all system_top

fixes incomplet portlist WARNING [Synth 8-350]
fixes undriven inputs WARNING [Synth 8-3295]

The change excludes the generated system.v and Xilinx files.
2018-08-10 17:00:11 +03:00
AndreiGrozav ebae8bf8c1 Remove interrupts from system_top for all xilinx projects
- remove interrupts from system_top
- for all suported carriers:
	- remove all interrupt bd pins
	- connect to GND all initial unconnected interrupt pins
- update ad_cpu_interrupt procedure to disconnect a interrupt from GND
before connectiong it to another pin.
2018-08-10 10:10:58 +03:00
Laszlo Nagy e2c75c015f axi_dmac: add tlast to the axis interface for Intel
This change adds the TLAST signal to the AXI streaming interface
of the source side for Intel targets.
Xilinx based designs already have this since the tlast is part of the
interface definition.

In order to make the signal optional and let the tool connect a
default value to the it, the USE_TLAST_SRC/DEST parameter is
added to the configuration UI. This conditions the tlast port on
the interface of the DMAC.

Xilinx handles the optional signals much better so the parameter
is not required there.
2018-07-06 16:30:30 +03:00
Adrian Costina bbb5a31994 Reviewed pinout of ZCU102 projects. fmcomms5 pin gpio_ad5355_lock location changed 2018-04-21 15:28:13 +03:00
Lars-Peter Clausen 2b914d33c1 Move Altera IP core dependency tracking to library Makefiles
Currently the individual IP core dependencies are tracked inside the
library Makefile for Xilinx IPs and the project Makefiles only reference
the IP cores.

For Altera on the other hand the individual dependencies are tracked inside
the project Makefile. This leads to a lot of duplicated lists and also
means that the project Makefiles need to be regenerated when one of the IP
cores changes their files.

Change the Altera projects to a similar scheme than the Xilinx projects.
The projects themselves only reference the library as a whole as their
dependency while the library Makefile references the individual source
dependencies.

Since on Altera there is no target that has to be generated create a dummy
target called ".timestamp_altera" who's only purpose is to have a timestamp
that is greater or equal to the timestamp of all of the IP core files. This
means the project Makefile can have a dependency on this file and make sure
that the project will be rebuild if any of the files in the library
changes.

This patch contains quite a bit of churn, but hopefully it reduces the
amount of churn in the future when modifying Altera IP cores.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-04-11 15:09:54 +03:00
Lars-Peter Clausen b20714bae2 Regenerate project top-level Makefiles
Removes a lot of boilerplate code.

Using the new scheme it is possible to add new projects or sub-projects
without having to re-generate any existing Makefiles.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-04-11 15:09:54 +03:00
Lars-Peter Clausen 377247a434 Regenerate project Makefiles using the new shared Makefile includes
This reduces the amount of boilerplate code that is present in these
Makefiles by a lot.

It also makes it possible to update the Makefile rules in future without
having to re-generate all the Makefiles.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-04-11 15:09:54 +03:00
Istvan Csomortani 318dcbb5d9 adrv9371x: Set up the defualt clock output control
The TX side runs on QPLL, and the RX and RX_OS runs on CPLL by default.
The OUTCLK frequency is the same as the REFCLK.

The main reason of this modification is that the links should come up
without any DPR access, after power up, using the default reference clock
configuration (122.88 MHz).
2018-04-11 15:09:54 +03:00
Istvan Csomortani 9a44ab921b adrv9371: Swap CSN lines to preserve consistency 2018-04-11 15:09:54 +03:00
Istvan Csomortani 7824f79fc0 adrv9371x:zcu102: Use explicit PACKAGE_PIN definitions for JESD204 lanes and reference clocks 2018-04-11 15:09:54 +03:00
Istvan Csomortani 425e803364 license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
Istvan Csomortani bd8c71c2ec adrv9371x:zcu102: Set DEVICE_TYPE to ultrascale 2018-04-11 15:09:54 +03:00
AndreiGrozav 502989c25f jesd_rst_gen:constraints: Remove invalid false path definitions
The constraint where added to remove timing problems on the reset path.

The constraint paths do not match anymore. The resets are used in a synchronous
way so we don't need the timing exceptions anyway.

Projects affected by this change:
  - daq3
  - adrv9739
  - ad6676evb
  - fmcadc5
  - daq2/kcu105
  - fmcadc2
  - adrv9371x
  - fmcomms11/zc706
  - fmcjesdadc1
2018-04-11 15:09:54 +03:00
AndreiGrozav dd8d6f90ee zcu102:all_projects: Delete required version tcl variable
All the ZCU102 projects will use the default tool version.
This setup was a temporary exception for hdl_2017_r1 release.
2018-04-11 15:09:54 +03:00
Istvan Csomortani a740b6012f Make: Use $(MAKE) for recursive make commands
This commit should resolve the issue #64.

Recursive make commands should always use the variable MAKE, not the explicit
command name ‘make’.
2018-03-07 07:40:19 +00:00
AndreiGrozav 8403ff17ec adrv9371x/kcu105: Use ultrascale type primitives in axi_clkgen IP 2018-02-13 17:33:38 +02:00
AndreiGrozav 2302d3516d adrv9371x:kcu105: Update transceiver configuration 2018-02-13 17:33:38 +02:00
Adrian Costina 73ef0fb48c adrv9371x: kcu105: Fix transceiver and clock placement 2018-02-13 17:33:38 +02:00
Michael Hennerich 2e59a70cdd adrv9371: Increase FCLK2 to 200MHz to support max sampling rates
This fixes an issue seen when using 307.2 MSPS on the Observation RX.

Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
2018-01-09 15:20:06 +01:00
AndreiGrozav a23c640180 Require Vivado 2017.2.1 for all zcu102 projects 2017-11-20 15:36:51 +00:00
AndreiGrozav f1e51a8b89 adrv9371x_zcu102: Fix rx_div_clk constraint placement 2017-11-20 15:36:51 +00:00
Adrian Costina b54dab33e0 Make: Update makefiles 2017-11-20 14:27:39 +02:00
Lars-Peter Clausen 46acdadb92 adrv9371x: Set correct transceiver type for UltraScale projects
Make sure that the axi_adxcvr instances are configured with the same
transceiver type as the util_adxcvr.

This is necessary for software to be able to detect the transceiver type
and support dynamic reconfiguration.

It is also necessary for correct eye scan support in the axi_adxcvr block.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-11-14 14:31:03 +01:00
Lars-Peter Clausen caac2ce588 adrv9371x: zcu102: Fix lane mapping
Fix the location assignment of the transceiver blocks to get the correct
lane mapping.

Note that the comments indicating the expected lane mapping are correct,
but the actual transceiver location assignments were not.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-11-14 14:31:03 +01:00
Lars-Peter Clausen f181e037cc adrv9371x: zcu102: Fix QPLL feedback divider
The external reference clock runs at 122.88 MHz by default. This means that
the QPLL feedback divider needs to be set to 80 so that the VCO is inside
the locking range (9.8 GHz - 16.375 GHz).

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-11-14 14:31:03 +01:00
AndreiGrozav 22808fa03c zcu102: Update to rev 1.0 2017-11-08 10:33:12 +02:00
Adrian Costina 37323e3444 adrv9371x: A10GX, added extra pipelining in the interconnect in order to improve timing 2017-10-20 13:46:22 +01:00
Istvan Csomortani be4e02aed9 adrv9371x/a10gx: Add external flash support 2017-10-06 08:43:58 +01:00
Istvan Csomortani a33f3178c2 adrv9371x/a10soc: For receive paths SYNC_TRANSFER must be enabled 2017-10-04 11:29:09 +01:00
Istvan Csomortani 700ed156ab [axi|avl]_dacfifo: Create a separate bypass module for altera/xilinx 2017-09-25 08:56:40 +01:00
Lars-Peter Clausen c3aa3e8a9c adrv9371: a10soc: Whitespace cleanup
Remove some extra end-of-line whitespace.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-09-05 13:47:49 +02:00
Lars-Peter Clausen e4988aa131 adrv9371x: altera: Convert to ADI JESD204
Convert the ADRV9371 project for Intel/Altera platforms to the ADI JESD204
framework.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-24 17:55:10 +02:00
AndreiGrozav d05ed29212 adrv9371x_zcu102: Initial commit 2017-08-22 15:48:03 +03:00
AndreiGrozav c0da4e6192 adrv9371x_kcu105: Initial commit 2017-08-22 15:41:49 +03:00
AndreiGrozav 1d67036305 adrv9371x/common: Remove ila_adc and ila_os_adc 2017-08-22 15:37:59 +03:00
AndreiGrozav 6fa45bb378 adrv9371x/common: Fix axi_ad9371_dacfifo/dac_rst assignamen 2017-08-22 15:37:59 +03:00
AndreiGrozav a64998c3ff adrv9371x: Separate ps7 assignaments from common
Move the assignaments/connections for ps7 from common/adrv9371_bd
to zc706/system_bd
2017-08-22 15:37:59 +03:00
Istvan Csomortani 7fa8498b3a adrv9371x: DAC_FIFO should get the dma_rst from sys_dma_rstgen 2017-08-22 09:16:21 +01:00
Lars-Peter Clausen 69a23ecde3 avl_adxcvr: Simplify TX lane mapping
Currently the TX lane mapping is implemented by having to connect tx_phy_s_* to
the tx_ip_s_* and the tx_phy_d_* to the tx_ip_d_* signals in the system
qsys file in the desired order.

Re-work things so that instead the lane mapping is provided through the
TX_LANE_MAP parameter. The parameter specifies in which order logical lanes
are mapped onto the physical lanes.

The appropriate connections are than made inside the core according to this
parameter rather than having to manually connect the signals externally.

In order to generate a 1-to-1 mapping the TX_LANE_MAP parameter can be left
empty.

This change slightly reduces the boiler-plate code that is necessary to
setup the transceiver.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-03 17:57:58 +02:00
Rejeesh Kutty 207f00a752 projects/ remove upack dma_xfer_in 2017-07-31 09:12:05 -04:00