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1290 Commits (dd79dfdc1257d86aa2d4de9e70f20057235dde26)

Author SHA1 Message Date
Lars-Peter Clausen dd79dfdc12 fmcadc5: Drop explicit axi_dmac clock synchronicity configuration 
The axi_dmac core is now capable of detecting whether its different parts
run in different clock domains or not. No need to configure it manually any
more.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2015-09-18 15:28:03 +02:00
Lars-Peter Clausen 7f5a22a75f fmcadc4: Drop explicit axi_dmac clock synchronicity configuration 
The axi_dmac core is now capable of detecting whether its different parts
run in different clock domains or not. No need to configure it manually any
more.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2015-09-18 15:28:01 +02:00
Lars-Peter Clausen 60490c4e2b fmcadc2: Drop explicit axi_dmac clock synchronicity configuration 
The axi_dmac core is now capable of detecting whether its different parts
run in different clock domains or not. No need to configure it manually any
more.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2015-09-18 15:27:59 +02:00
Lars-Peter Clausen 6c7316fbd0 daq3: Drop explicit axi_dmac clock synchronicity configuration 
The axi_dmac core is now capable of detecting whether its different parts
run in different clock domains or not. No need to configure it manually any
more.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2015-09-18 15:27:56 +02:00
Lars-Peter Clausen 7184827d68 daq2: Drop explicit axi_dmac clock synchronicity configuration 
The axi_dmac core is now capable of detecting whether its different parts
run in different clock domains or not. No need to configure it manually any
more.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2015-09-18 15:27:54 +02:00
Lars-Peter Clausen f1fb599eb1 cn0363: Drop explicit axi_dmac clock synchronicity configuration 
The axi_dmac core is now capable of detecting whether its different parts
run in different clock domains or not. No need to configure it manually any
more.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2015-09-18 15:27:51 +02:00
Lars-Peter Clausen 6d87f537da cftl_cip: Drop explicit axi_dmac clock synchronicity configuration 
The axi_dmac core is now capable of detecting whether its different parts
run in different clock domains or not. No need to configure it manually any
more.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2015-09-18 15:27:49 +02:00
Lars-Peter Clausen 1c603b830e ad9467_fmc: Drop explicit axi_dmac clock synchronicity configuration 
The axi_dmac core is now capable of detecting whether its different parts
run in different clock domains or not. No need to configure it manually any
more.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2015-09-18 15:27:47 +02:00
Lars-Peter Clausen 960c711f3b ad9434_fmc: Drop explicit axi_dmac clock synchronicity configuration 
The axi_dmac core is now capable of detecting whether its different parts
run in different clock domains or not. No need to configure it manually any
more.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2015-09-18 15:27:44 +02:00
Lars-Peter Clausen 7be1f62b8b ad9265_fmc: Drop explicit axi_dmac clock synchronicity configuration 
The axi_dmac core is now capable of detecting whether its different parts
run in different clock domains or not. No need to configure it manually any
more.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2015-09-18 15:27:25 +02:00
Lars-Peter Clausen 0f553a08e8 ad6676evb: Drop explicit axi_dmac clock synchronicity configuration 
The axi_dmac core is now capable of detecting whether its different parts
run in different clock domains or not. No need to configure it manually any
more.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2015-09-18 15:27:21 +02:00
Adrian Costina 0021c7869d kc705: Deactivated narrow burst support, as it's not needed 2015-09-16 19:02:17 +03:00
Adrian Costina 70cea5b14e fmcomms1: Removed ILA 2015-09-16 18:51:40 +03:00
Adrian Costina 63aaa58861 ad9265_fmc: Updated project, removed ILA related clocks 2015-09-11 11:27:58 +03:00
Istvan Csomortani a679251d7d Makefiles: Update Make 2015-09-09 17:13:19 +03:00
Istvan Csomortani f3eca48533 pzsdr_rfsom: Update project with the new TDD sync interface 2015-09-09 12:37:52 +03:00
Istvan Csomortani 510f1cfdd9 fmcomms2_zc706: Update project with the new TDD sync interface 2015-09-09 12:35:22 +03:00
Adrian Costina f428d8bde9 adv7511: KC705, updated design so that the axi_hdmi_dma core has memory connection datawidth of 512 2015-09-08 16:43:40 +03:00
Adrian Costina d81d8238a9 kc705: Updated mig project file 2015-09-08 16:42:23 +03:00
Adrian Costina 2757cd8baf adv7511: AC701 fixed system top 2015-09-07 16:48:10 +03:00
Rejeesh Kutty 214f5b18c1 no-trace option 2015-09-03 16:16:31 -04:00
Rejeesh Kutty 00a55ded00 ibert to jesd-gt change 2015-09-03 16:16:30 -04:00
Rejeesh Kutty 77ee3c4cbc ibert to jesd-gt change 2015-09-03 16:16:28 -04:00
Rejeesh Kutty dbf7c154b2 no-trace option 2015-09-03 16:16:27 -04:00
Rejeesh Kutty e2aca435e5 ibert-to-jesd-gt change 2015-09-03 16:16:25 -04:00
Rejeesh Kutty f1d416a98b daq2/a10gx- ethernet fix 2015-09-02 14:31:15 -04:00
Rejeesh Kutty 1fff1076b1 daq2/a10gx- ethernet fix 2015-09-02 14:31:15 -04:00
Rejeesh Kutty 01c0fdc809 daq2/a10gx- ethernet fix 2015-09-02 14:31:15 -04:00
Istvan Csomortani 1ecd615f92 common/mitx045 : Fix the vdma interface of axi_hdmi_core 2015-09-02 16:33:30 +03:00
Lars-Peter Clausen 9fb336e464 usdrx1: Add DDR FIFO 
The converters on the usdrx1 generate 2.5GB/s. This more than we can
transport over the HP interconnects to the system memory.

Add a dedicated DDR FIFO to design which can be used to buffer the data
before it is transferred to the main memory.

Also increase the interconnect clock rate from 100MHz to 200MHz and the DMA
FIFO size from 4 to 8, so we can transfer the captured data faster to the
main memory.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2015-09-01 11:29:36 +02:00
Lars-Peter Clausen bbada6ed8f usdrx1: Add overflow flag to ILA 
It's useful to know if and when a overflow happens.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2015-09-01 11:29:36 +02:00
Lars-Peter Clausen c67aecc1eb usdrx1: Disable SYNC_TRANSFER_START for the DMA 
There is no sync signal in this design, so the flag needs to be set to 0.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2015-09-01 11:29:36 +02:00
Rejeesh Kutty 9b37d6bfe7 pzslb- updates - wip 2015-08-31 15:41:29 -04:00
Rejeesh Kutty 49430dc2b0 pzslb- copy 2015-08-31 15:41:27 -04:00
Rejeesh Kutty 879a75a690 pzslb- copy 2015-08-31 15:41:26 -04:00
Rejeesh Kutty fdc3dbb805 pzslb- copy 2015-08-31 15:41:25 -04:00
Rejeesh Kutty fc79af6edc pzslb- common 2015-08-31 15:41:24 -04:00
Rejeesh Kutty f005de9ee2 pzslb- added 2015-08-31 15:41:23 -04:00
Rejeesh Kutty a67ae238f8 rfsom-ps7- ddr settings 2015-08-31 15:39:45 -04:00
Rejeesh Kutty 212235189f hdmi-tx- signal name changes 2015-08-28 13:48:33 -04:00
Rejeesh Kutty 0e20277bc1 hdmi-tx- signal name changes 2015-08-28 13:48:33 -04:00
Rejeesh Kutty 93fe70790d hdmi-tx- signal name changes 2015-08-28 13:48:33 -04:00
Rejeesh Kutty 810fced1ec hdmi-tx- signal name changes 2015-08-28 13:48:33 -04:00
Rejeesh Kutty 01852a14de hdmi-tx- signal name changes 2015-08-28 13:48:33 -04:00
Rejeesh Kutty 7a1df720e2 rfsom- tdd ensm io changes 2015-08-27 16:26:18 -04:00
Rejeesh Kutty 6e90ba24e4 rfsom- add rgmii iodelay constraints 2015-08-27 16:26:17 -04:00
Rejeesh Kutty 15be942b74 daq2-a10gx- ignore cpu2ddr-io paths 2015-08-27 13:54:05 -04:00
Rejeesh Kutty a92e049e8f fmcomms2_bd- another attempt at ila width 2015-08-27 13:17:08 -04:00
Rejeesh Kutty 90e4cadf4b daq2/kcu105- xcvr pin loc 2015-08-27 12:40:44 -04:00
Rejeesh Kutty b8f9b7040d fmcomms2- tdd ila fixes 2015-08-27 11:55:41 -04:00