Commit Graph

2130 Commits (ddfbdfd2f748b4171db79b8101dac220b74f3143)

Author SHA1 Message Date
Rejeesh Kutty ddfbdfd2f7 pzsdr1/pzsdr2- ccbox added tws 2017-04-18 11:37:23 -04:00
Adrian Costina 5a7aa80145 m2k: zed, cleaned up some warnings 2017-04-18 17:17:11 +03:00
Adrian Costina 919010e85f m2k: ip automatic version update 2017-04-18 15:12:07 +03:00
Adrian Costina b05505a1c3 m2k: Move the BRAM generation outside of the variable fifo IP 2017-04-18 12:17:40 +02:00
Lars-Peter Clausen 5f83e20d33 m2k: standalone: Rework PS7 clocking
At the moment the PS7 is using three PLLs to generate its clocking tree.
One for the DDR, one for the ARM and one for the IO. This allows to run all
components at their respective maximum clock and extract maximum
performance from all components.

With some slight modifications it is possible to trade maximum performance
for a reduction in power consumption by using the same PLL for all three
sets of components and disabling the other two PLLs.

The CPU is now running at 500MHz rather than 666MHz and the DDR memory at
500MHz rather than 533MHz. This reduces power consumption by ~125mW.

This is OK since neither of them is a bottleneck for overall system
performance.

In addition software will downclock the CPU to 250MHz when full performance
is not required.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:40 +02:00
Lars-Peter Clausen 3b748d8252 m2k: standalone: Disable 200MHz clock
The 200 MHz clock was only used as the IODELAY controller clock. Since the
design does not use any IODELAYs anymore this clock can be removed.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:40 +02:00
Lars-Peter Clausen 63dfec25c1 m2k: standalone: Disable 2nd PS7 reset port
This reset is not used in the design, so remove it.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:40 +02:00
Adrian Costina 189e9194c8 m2k: Standalone, enabled power optimization 2017-04-18 12:17:40 +02:00
Adrian Costina 8b76c34dea scripts: Created ADI_POWER_OPTIMIZATION parameter for enabling power optimizations in the implementation stage 2017-04-18 12:17:40 +02:00
Adrian Costina 07e52b4566 m2k: Connect logic_analyzer path to clk_out instead of clk
- this allows for the clock switching to be done inside axi_logic_analyzer core
2017-04-18 12:17:39 +02:00
Lars-Peter Clausen 610cc3affa m2k: standalone: Disable DMA debug registers
The debug register logic for the DMA take up a fair amount of resources.
Disabling them frees up space in the FPGA and also helps a bit with power.
Since those registers are mainly useful in development and not so much in
production the change shouldn't have any visible external effects.

It is possible to re-enable the debug registers by setting DEBUG_BUILD=1.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:39 +02:00
Lars-Peter Clausen c9f863f189 m2k: standalone: Set static switching activity for the reset signals
The global reset signals are only asserted for a short moment during system
startup and deasserted during normal operation, which is the case we care
about for power analysis. Giving them a static switching probability
indicating that they are always de-asserted will yield better results for
power analysis.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:39 +02:00
Lars-Peter Clausen b206f8f37a m2k: Disable AD9963 core RX datapath again
The RX datapath has a lot of things (IQ correction, DC filter, ...) that
take up a lot of space which are all not really needed in this project. So
disable the RX datapath.

It was previously enabled because the ad9963 core did not perform
sign-extension on the ADC data signal when the datapath was disabled. But
this has now been addressed.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:39 +02:00
Lars-Peter Clausen c1ba57f808 m2k: Rework clocking domains
At the moment the register map fabric and DMA system memory side are
clocked by the 100MHz sys_cpu_clk. While this works fine that is a lot
faster than the clock has to run. There are only a few 100 register map
accesses per seconds at most and they are not on timing critical paths. The
penalty from clocking them at a lower rate is negligible for the overall
system performance.

The maximum clock rate for the DMAs is determined by the throughput
requirements. This is 200 Mbytes/s for the logic analyzer, pattern
generator and each of the DAC DMAs and 400 Mbytes/s for the ADC DMA.

The DMA datapath width is 64-bit so the required clock rates are 25MHz and
50MHz respectively. Some headroom is required to accommodate for occasional
bubble cycles on the data bus and the difference in reference clocks for
the converter and processing system.

The sys_cpu_clk is reduced to 27.8MHz which is fast enough for all but the
ADC DMA. For the ADC DMA a new clock domain running at 55.6 MHz is
introduced.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:39 +02:00
Lars-Peter Clausen 2eaf931e07 m2k: Replace logic analyzer MMCM
The MMCM generating the logic analyzer clock unfortunately consumes a
disproportionately large amount of power compared to the rest of the
design.

Replace it by sourcing the logic analyzer clock from one of the Zynq FCLKs.
The IO PLL is running anyway so the power requirement is much lower.

For the time being this means we loose the ability to source the clock from
an external pin. But that feature is not supported by software at the
moment anyway. We'll bring it eventually when required.

This changes reduces power consumption by roughly 100mW.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:39 +02:00
Lars-Peter Clausen e616c8da0b m2k: Remove channel pack core for now
We always have both ADC channels enabled and the cpack core takes up a fair
amount of space, so remove it for now. Might come back later when we really
need it.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:39 +02:00
Adrian Costina efa2d0c006 m2k: Connected adc/dac resets to decimation/interpolation cores 2017-04-18 12:17:39 +02:00
Adrian Costina 500112f79b m2k: Renamed l_clk to adc_clk and rst to adc_rst 2017-04-18 12:17:39 +02:00
Adrian Costina 6a49aefb6c m2k: Updated project to use new tx path with serdes 2017-04-18 12:17:39 +02:00
Lars-Peter Clausen b58a5c37eb m2k: Reduce AXI interconnect utilization
Use the new axi_rd_wr_combiner module to ... the read and write DMA
interfaces into a single interface. This allows the AXI interconnect
completely optimize itself away and reduce the overall resource utilization
of the project.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:39 +02:00
Adrian Costina 71394ee465 kcu105: ip automatic version update 2017-04-18 11:59:54 +03:00
Adrian Costina 942d69a30c Makefiles: Change MMU enabling parameter for altera designs from MMU to NIOS2_MMU 2017-04-18 10:57:16 +03:00
Adrian Costina 8e0c87e089 pluto: cleaned up some warnings 2017-04-18 10:34:13 +03:00
Adrian Costina f3c0be0868 motcon2_fmc: cleaned up some warnings 2017-04-18 10:33:13 +03:00
Adrian Costina 6e14cdb5f4 cftl_std: cleaned up some warnings 2017-04-18 10:32:28 +03:00
Adrian Costina d585d65692 cftl_cip: cleaned up some warnings 2017-04-18 10:29:20 +03:00
Adrian Costina 20672a3a8b mitx045: ip automatic version update 2017-04-14 17:46:25 +03:00
Adrian Costina 954037a716 microzed: ip automatic version update 2017-04-14 17:24:24 +03:00
Adrian Costina ebc04bcd9c usdrx1: ip automatic version update 2017-04-14 17:16:35 +03:00
Adrian Costina 24b797f1a6 motcon2: ip automatic version update 2017-04-14 17:11:08 +03:00
Adrian Costina 4981e6e525 usb_fx3: ip automatic version update 2017-04-14 16:55:30 +03:00
Adrian Costina c419b0042b pluto: ip automatic version update 2017-04-14 16:55:07 +03:00
Adrian Costina 79174422b6 imageon: ip automatic version update 2017-04-14 16:54:42 +03:00
Adrian Costina 4bda0c3a1a cftl_cip: ip automatic version update 2017-04-14 16:54:07 +03:00
Adrian Costina afe8b071a3 cftl_std: ip automatic version update 2017-04-14 16:53:10 +03:00
Istvan Csomortani 1c23cf4621 all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
AndreiGrozav 04a4001dba Ip automatic version update: fmcadc2, fmcadc5 2017-04-12 19:03:16 +03:00
AndreiGrozav 627f78ec19 Ip automatic version update: common/board
- vc707
- zc702
- zed
2017-04-12 19:03:16 +03:00
Rejeesh Kutty 6d2b3bc1c7 adi_project- try something simple first 2017-04-11 14:27:35 -04:00
Rejeesh Kutty 1d9a8a24dc adi_board- create_bd_cell replacement 2017-04-11 14:26:02 -04:00
AndreiGrozav bc9483c5a2 Ip automatic version: Update ad*/common/ad*_bd.tcl
ad6676evb/common/ad6676evb_bd.tcl
ad7616_sdz/common/ad7616_bd.tcl
ad7768evb/common/ad7768evb_bd.tcl
ad9265_fmc/common/ad9265_bd.tcl
ad9434_fmc/common/ad9434_bd.tcl
ad9467_fmc/common/ad9467_bd.tcl
ad9739a_fmc/common/ad9739a_fmc_bd.tcl
adrv9371x/common/adrv9371x_bd.tcl
adv7511/common/adv7511_bd.tcl
fmcadc4/common/fmcadc4_bd.tcl
2017-04-10 18:52:37 +03:00
Rejeesh Kutty 454e6c0382 daq2- ad-ip-instance & ad-ip-parameter 2017-04-06 13:04:53 -04:00
Rejeesh Kutty 2535165461 xilinx- ad-ip-instance & ad-ip-parameter 2017-04-06 13:04:19 -04:00
Rejeesh Kutty 80f93e6a31 zc706- ad-ip-instance & ad-ip-parameter 2017-04-06 13:03:22 -04:00
Rejeesh Kutty 820874ef93 adi_board- add auto ip version handling 2017-04-06 13:02:17 -04:00
Lars-Peter Clausen e04793b6eb m2k: standalone: Assign 0 to unused GPIO inputs
To avoid warnings from the tools assign 0 to the unused GPIO inputs.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-03-30 11:16:25 +02:00
Rejeesh Kutty 8eb1dd0a8b adrv9371x/altera- xilinx/chip-select consistency 2017-03-29 12:59:09 -04:00
Lars-Peter Clausen 24a7d8ea9d m2k: Remove redundant s_axi_{aclk,aresetn} assignment
ad_cpu_interconnect will make sure to connect the clock and the reset of
the AXI interface. Remove the redundant manual assignments.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-03-28 11:14:48 +02:00
Rejeesh Kutty deb8635854 adrv9371x/altera- gpio equivalency fix 2017-03-27 16:37:55 -04:00
Rejeesh Kutty 8f1564a9c4 adrv9371x/a10gx- gpio matching 2017-03-27 13:51:45 -04:00