ac2e5a9dac
constraints: Update constraints
...
Xilinx recommends that all synchronizer flip-flops have
their ASYNC_REG property set to true in order to preserve the
synchronizer cells through any logic optimization during synthesis
and implementation.
2017-02-24 13:43:32 +02:00
35f660fe06
fmcjesdadc1/vc707- constraint clean-up
2017-02-02 15:05:49 -05:00
1156aeac16
ad_sysref_gen: Update SYSREF related constraints
2016-12-19 18:07:05 +02:00
8d799d0316
fmcjesdadc1: Intergrate ad_sysref_gen into project
2016-12-19 13:37:29 +00:00
a54092c9bb
fmcjesdadc1: Update projects to xcvr framework
...
This commit contains modifications for Xilinx only
2016-11-10 10:59:52 +02:00
59fbd99fdb
fmcjesdadc1: Added clock constraint for the ADC path
2016-01-22 15:46:20 +02:00
7f9c526683
fmcjesdadc1: VC707 update project
2015-09-24 19:50:14 +03:00
11379939d0
fmcjesdadc1: VC707, Updated project to the latest framework
2015-03-30 18:08:19 +03:00
2ce7695bf7
fmcjesdadc1: Initial commit of VC707 version
2014-09-01 18:47:01 +03:00
Istvan Csomortani
Rejeesh Kutty
Adrian Costina