Commit Graph

169 Commits (de0edc2083818de8c086b1535a4f5d36684f2300)

Author SHA1 Message Date
Lars-Peter Clausen de0edc2083 axi_dmac: src_fifo_inf: Clear pipeline when no transfers are active
Clear the pipeline when no transfers are active to make sure that we do not
get residual data on the first sample for the next transfer.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-16 21:02:05 +02:00
Lars-Peter Clausen c927e90ee1 axi_dmac/axi_fifo: Add missing file
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-15 21:04:57 +02:00
Lars-Peter Clausen 17a993032b util_dac_unpack: Make number of channels and channel width configurable
Always using 128bit for the input word unnecessarily increases the DMA
alignment requirements. This breaks existing software which assumes that the
DMA alignment requirement is 64bit.

So make it configurable whether we want 8 or 4 channels and while we are at
it also make the channel width configurable.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-12 16:14:04 +02:00
Adrian Costina 61f21a17b3 fmcomms2:c5soc project upgraded with util_dac_unpack 2014-09-11 15:13:09 -04:00
Lars-Peter Clausen 3162540b03 axi_ad9361: Remove the Altera toplevel wrapper
By setting the AXI controler interface type from axi4 to axi4lite we can use
the normal toplevel file with only a simple modification to add the awprot
and arprot signals.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-11 12:29:13 +02:00
Lars-Peter Clausen 36422f0454 axi_dmac: Remove Altera toplevel wrapper
We can remove the Altera toplevel wrapper if we switch the axi4 control bus
to axi4lite and add the few missing signals that are required by the Altera
interconnect to both the control and the data buses.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-11 12:28:14 +02:00
Lars-Peter Clausen b877cea2ed up_axi: Add parameter to configure the internal address width
Not all peripherals need 14 bit of address space.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-11 12:26:40 +02:00
Lars-Peter Clausen 41cc92ef49 Remove BASEADDR/HIGHADDR parameters
This is unused and unneeded. The AXI interconnect will make sure that a
peripheral only gets requests that are meant for it, there is no need to
check the address in the peripheral itself.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-11 12:26:37 +02:00
Lars-Peter Clausen 6ad589475a up_axi: Prevent read and write requests from racing against each other
Make sure that if a read and a write request arrive on the very same clock
cycle to only accept one of them. The simple solution chosen here is to only
accept the write request when this happens and delay the acceptance of the
read request until the write request is finished.

This solution is not fair since a write request will always take precedence,
which in theory allows the write bus to starve the read bus. But in practice
we should never see that many write requests that we are unable to answer
the read request.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-10 13:04:05 +02:00
Lars-Peter Clausen 18a506b3ca up_axi: Wait for the transaction to fully finish before releasing up_axi_access
Wait for the master to accept the response for the current transaction
before we allow a new transaction to start.

This fixes problems in case the master is not ready to accept the response
when we make it available.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-10 13:03:52 +02:00
Lars-Peter Clausen 0da7b6eaa1 axi_dmac: axi_dmac_alt.v: Set default transfer length width to 24
This is the same as the default value in axi_dmac.v

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-09 15:07:35 +02:00
Lars-Peter Clausen a4b9b1254a axi_ad9361/axi_dmac: Fix altrea AXI wrapper rid/wid handling
We must make sure that the response ID is the same as the request ID when we
accepted the request. Otherwise we might respond with the wrong ID and the
system will lockup.

Also set rlast to 1 instead of 0.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-09 15:05:06 +02:00
Lars-Peter Clausen 50faf0c53a Remove executable flags from non-exectuable files 2014-09-09 15:05:06 +02:00
acozma 0966366514 motor_control: Updated the FOC IP 2014-09-08 15:52:18 +03:00
acozma 6e389b8c47 motor_control: Updated the FOC IP and the encoder connections to the IP 2014-09-06 15:58:03 +03:00
Adrian Costina acde4f2c9a axi_dmac: Added fix to work with motor_control 2014-09-03 12:10:34 +03:00
Adrian Costina dfb94f7b68 motor_control: Modified foc_controller to be compatible with other cores 2014-09-03 12:09:37 +03:00
acozma d08d0cd70b motor_control: added the MW FOC IP and updated the design 2014-09-01 18:35:21 +03:00
Adrian Costina a773cc4992 usdrx1: updated project
ad_jesd_align wasa updated to be able to work with frames that have more than 4 octets per frame
2014-09-01 15:18:39 +03:00
Adrian Costina cf660c126d util_adc_pack: Fixed problems when working in 4 channels mode 2014-08-29 13:51:40 +03:00
Rejeesh Kutty da913864c9 ad9671_fmc: updates to match recent core changes 2014-08-28 13:16:52 -04:00
Rejeesh Kutty 272874f6ad ad9652: pnmon fixes 2014-08-27 10:44:38 -04:00
Adrian Costina 31002c404c util_adc_pack: Added parameters for configuring data width and number of channels
Valid values for the number of channels is 4 or 8
Valid values for datawidth is 16 or 32
2014-08-27 14:47:57 +03:00
Adrian Costina 58fa0776c9 axi_dmac: Added patch to fix issue on altera systems 2014-08-26 16:24:34 +03:00
Rejeesh Kutty 5f21f54463 fmcjesdadc1: zc706 version 2014-08-25 14:28:57 -04:00
Rejeesh Kutty fe1eaefcff fmcomms1: zc706 2014-08-22 09:08:55 -04:00
Rejeesh Kutty 280260e54c c5soc: dmac separated slave and master id widths 2014-08-22 09:08:54 -04:00
Rejeesh Kutty b481df0b5f library: local constraints async groups 2014-08-14 15:09:51 -04:00
Rejeesh Kutty 01963b01fc jesd_gt: local constraints 2014-08-14 15:09:49 -04:00
Rejeesh Kutty 9438e2a9e0 spdif: constraints file added 2014-08-14 15:09:48 -04:00
Rejeesh Kutty 1396a215e5 library: local constraints 2014-08-14 15:09:47 -04:00
Rejeesh Kutty 39bb7ca231 a5soc: fmcjesdadc1+hdmi version 2014-08-14 09:05:38 -04:00
Istvan Csomortani 2b15c7313e ad_dcfilter: Fix filter loopback 2014-08-12 14:42:10 +03:00
Rejeesh Kutty a5e3a07375 dma: altera fix id assignments 2014-08-11 16:46:36 -04:00
Istvan Csomortani 9dfbf4a9a6 prcfg: Update the prcfg logic to the new ad9361 interface 2014-08-05 17:54:37 +03:00
Rejeesh Kutty 08a12aaf23 library: register map updates on 9467, 9643 and 9671 2014-07-31 15:19:45 -04:00
Rejeesh Kutty dfd11cb809 ad9467: register map changes 2014-07-30 15:31:09 -04:00
Rejeesh Kutty c215eab696 ad9122: register map updates 2014-07-30 11:32:15 -04:00
Rejeesh Kutty b97bdcdc23 ad9122: register map updates 2014-07-30 11:32:13 -04:00
Adrian Costina a2b728b91e util_adc_pack: added extra registers to meet timing.
Util_dac_unpack: fixed issue regarding changing from 1 channel to 2
2014-07-25 17:41:47 +03:00
Adrian Costina 26a019ae6e util_adc_pack: Fixed issue regarding changing from 1 channel to 2 2014-07-25 10:20:49 +03:00
Rejeesh Kutty 59759a8ab3 c5soc: working hdl version 2014-07-24 20:51:41 -04:00
Rejeesh Kutty 6346017763 c5soc: changed to alt_lvds - 250M is too high for cyclone v 2014-07-24 20:51:40 -04:00
Adrian Costina 7000897031 fmcomms2, fmcomms5: updated util_adc_pack and util_dac_unpack
The cores now support up to 8 channels, in 1, 2, 4, 8 channel active configuration
2014-07-24 19:57:22 +03:00
Rejeesh Kutty 701dc96016 up_dac_channel: make iq cor coeff(s) tc 2014-07-24 10:10:24 -04:00
Istvan Csomortani 191f994e79 prcfg: Fixed the PRBS lock issue on BIST 2014-07-24 09:41:13 +03:00
Istvan Csomortani db1c931736 ad9625_plddr: PL DDR3 fixes
- Modified the axi slave interface handler
  - Increased the rfifo_mem input depth to prevent overflow
2014-07-23 19:34:44 +03:00
Istvan Csomortani 4da8100fe5 ad9625_plddr: Delete trailing whitespaces. 2014-07-23 19:31:07 +03:00
Adrian Costina 54b2cd74bf motor_control: cores modified so they can compile with the new common files 2014-07-23 11:58:50 +03:00
Rejeesh Kutty c0e31aa6c2 daq2: latest hardware 2014-07-21 09:06:57 -04:00