544e2b8ad0
util_pulse_gen: Pulse should not be generated if module is in reset
2019-08-08 14:26:07 +03:00
75e4c844ba
util_pulse_gen: Optimise design in order to improve timing
2019-08-08 14:26:07 +03:00
0680e44330
system_id: deployed ip
2019-08-06 16:53:11 +03:00
4fe5f007cb
system_id: added axi_sysid ip core and tcl
2019-08-06 16:53:11 +03:00
ab3d43be71
up_axi.v: fixed bus width definition
...
fixed axi_dma_regmap.v bus width missmatch
2019-08-06 13:45:54 +03:00
f2d2092297
axi_dacfifo: Add don't touch for the constraints to apply
2019-08-01 18:15:45 +03:00
c3739b1f30
Fix copy-paste typo in *_ip.tcl
...
- axi_ad9162
- axi_ad9434
- axi_ad9625
- axi_hdmi_tx
2019-07-29 15:37:30 +03:00
fe09acaa2f
up_axi_update: ADDRESS_WIDTH parameter is now a localparam
...
ADDRESS_WIDTH is now AXI_ADDRESS_WIDTH - 2;
up_axi instantiations will set AXI_ADDRESS_WIDTH instead of ADDRESS_WIDTH;
2019-07-26 11:58:58 +03:00
fa610d36c6
ad_ghdl_dir: Fix global variable name
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In #PR318 the global variable $ad_phdl_dir name were changed to
$ad_ghdl_dir.
2019-07-23 10:29:37 +01:00
6a721c0bf0
adi_env: Update system level environment variable definition
...
Our internal repository was changed from phdl to ghdl. Update the
adi_env.tcl scripts and other scripts, which depends on the $ad_ghdl_dir
variable. This way the tools will see all the internal IPs too.
2019-07-22 11:00:45 +03:00
3031ec3bdd
adi_jesd204: Move some leftover files to intel directory
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These file were left in the old library directory, move them to the new
library/intel directory.
2019-07-10 10:57:12 +01:00
1f1b2b4fa3
axi_dmac:axi_dmac_ip: Fix AXI Stream signals bundle
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The unused AXI stream signals have to be added to the AXIS interface so
they don't hang loose on the IP in the block design.
2019-07-08 16:08:06 +03:00
bb8912b766
axi_hdmi_tx: Update parameter name
2019-06-29 06:53:51 +03:00
76620bc890
avl_adxcvr: Rename variables with alt_* pre-fix
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- alt_sys_clk -> sys_clk
- alt_xcvr_rst -> xcvr_rst
- alt_ref_clk -> ref_clk
- alt_fpll_rst_cntrol -> fpll_rst_control
- alt_core_pll -> core_pll
- alt_core_clk -> core_clk
- alt_rst_cntrol -> rst_control
- alt_lane_pll -> lane_pll
- alt_ip -> jesd204_ip
- alt_xphy -> avl_xphy
- alt_phy_* -> phy_*
2019-06-29 06:53:51 +03:00
6a42f54b1e
axi_ad9361/intel: Rename varibles with alt_* pre-fix
2019-06-29 06:53:51 +03:00
0f7a3b953a
scripts/adi_ip_intel: Rename the ad_alt_intf to ad_interface
2019-06-29 06:53:51 +03:00
04ce10a570
cosmetics: Change Altera to Intel in comments
2019-06-29 06:53:51 +03:00
2f0dbe6151
intel_mem_asym: Rename the alt_mem_asym to intel_mem_asym
2019-06-29 06:53:51 +03:00
1e074726db
intel_serde: Rename alt_serdes to intel_serdes
2019-06-29 06:53:51 +03:00
b0fbe1bb57
util_clkdiv: Seperate the IP source into an intel and xilinx version
2019-06-29 06:53:51 +03:00
84bd50d437
alt_ifconv: Remove unused IP
2019-06-29 06:53:51 +03:00
d5e5fcf17a
alt_mul: Remove unused IP
2019-06-29 06:53:51 +03:00
5329458a62
library/scripts: Rename adi_ip_alt.tcl to adi_ip_intel.tcl
2019-06-29 06:53:51 +03:00
363494ab9c
library/scripts: Rename adi_ip.tcl to adi_ip_xilinx.tcl
2019-06-29 06:53:51 +03:00
79b6ba29ce
all: Rename altera to intel
2019-06-29 06:53:51 +03:00
d79fa179a3
spi_engine: Fix sync_bit instances
2019-06-28 11:18:29 +03:00
ba4a915af0
ad40xx/zed: fixed system_bd
...
spi_engine_execution: fixed sdo default
2019-06-28 11:18:29 +03:00
42b14f341a
axi_spi_engine: Generate false paths only on ASYNC_CLK mode
2019-06-28 11:18:29 +03:00
f4de1fecdc
spi_engine_execution: Add an additional register stage for the physical SPI
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The main reason is to improve timing when the SPI clock is more than
50 MHz. (the SPI Engine's spi_clk is more than 100MHz)
2019-06-28 11:18:29 +03:00
77ffa1f8ac
util_dec256sinc24b: Fix the accumulator
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Do a similar fix as for the decimation stage. (ab2788)
2019-06-28 11:18:29 +03:00
158b018f58
spi_execution: Improve timing by defining resets for the shift registers
2019-06-28 11:18:29 +03:00
d802ece39e
spi_engine: Reindent execution module source code
2019-06-28 11:18:29 +03:00
9ab88f1200
ad40xx: Initial commit
2019-06-28 11:18:29 +03:00
94f8d1b424
util_axis_upscale: Sign extension must be done separately for each channel
2019-06-28 11:18:29 +03:00
5f8269da03
spi_egine: Add a new register for dynamic transfer length configuration
2019-06-28 11:18:29 +03:00
40fbb37d6f
spi_engine: Add additional synchronization FIFO's to axi_spi_engine
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Add additional synchronization FIFOs to several interfaces of the
axi_spi_engine module, to prevent metastability and timing issues in
case when the system clock and the SPI clock are asynchronous.
2019-06-28 11:18:29 +03:00
91801bfe0d
spi_engine: Update the ad_rst instance
2019-06-28 11:18:29 +03:00
68c1f92066
spi_engine: Add a CDC fifo for the SYNC interface too
2019-06-28 11:18:29 +03:00
a19f6197cc
spi_engine: Fix indentation of axi_spi_engine.v
2019-06-28 11:18:29 +03:00
b81c8373e5
spi_engine: In read only mode SDO line should stay in its default level
2019-06-28 11:18:29 +03:00
85bbf95c57
spi_engine/offload: SDI_READY should be asserted while offload is inactive
2019-06-28 11:18:29 +03:00
746f457ef9
spi_engine: Software reset should reset the offload control registers too
2019-06-28 11:18:29 +03:00
19655b8092
spi_engine: Define SDO default state
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There are devices where the SDO default state, between transactions, is
not GND, rather VCC.
Define a parameter, which can be used to set the default state of the
SDO line.
2019-06-28 11:18:29 +03:00
45a08a004d
spi_engine:execution: Set default SDI driver value for all ports
2019-06-28 11:18:29 +03:00
8fb6fb329e
util_dec256sinc24b: Fix the differentiator
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Move the subtraction outside of the always block. In this way we're not adding
an additional delay element on to the output of the differentiator,
which brakes the transfer function of the filter.
2019-06-28 11:18:29 +03:00
a15afa6c03
util_dec256sinc24b: Avoid generated clock from logic
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Do not use word_clk, create a clock enable signal instead.
2019-06-28 11:18:29 +03:00
59ce663479
util_dec256sinc24b: Fix resets
2019-06-28 11:18:29 +03:00
6668accc96
ad7405 : Initial commit
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This project is an inital version of the ADuM7701 (CMOS) or AD7405 (LVDS)
reference board.
2019-06-28 11:18:29 +03:00
65fea6c4c0
ad_ip_jesd204_tpl_dac: Fix up_axi instantiation
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This patch will fix the following warning:
[Synth 8-689] width (16) of port connection 'up_axi_awaddr'
does not match port width (12) of module 'up_axi'
2019-06-27 13:47:00 +03:00
acf6d618dd
util_clkdiv: fix for multiple instances
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Vivado propagates and auto derives the clocks, however if multiple
instances of this components are used the names of the propagated clock
change while the constraint file has fixed name which will match only
the clocks from the first instance letting the second instance of the
clock div without exception.
2019-06-27 10:33:51 +03:00
fd6a395347
axi_fmcadc5_sync: rename generated spi clock
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Rename the clock so it won't conflict with the main spi clock name.
2019-06-26 16:10:07 +03:00
1c99fde06b
axi_ad9361: Fix Intel interface - technology encoding update
2019-06-25 15:40:51 +03:00
01081c93e8
axi_ad9361: Fix the interface for Intel devices
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Use missing MIMO_ENABLE parameter, which will insert
and additional de-skew logic to prevent timing issues coming from
the clock skew differences of two or multiple AD9361.
2019-06-25 15:40:51 +03:00
81bcf9f6fc
util_adxcvr: Cleanup whitespaces for GTY4 instantiations
2019-06-25 15:35:49 +03:00
369974f2e7
axi_fan_control: updated ip
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fixed tacho evaluation bug; updated fsm;
2019-06-14 17:08:38 +03:00
92a0e8eb1e
util_adcfifo: Fix SDC cosntraints
2019-06-13 10:59:43 +03:00
78b14f9803
axi_ad9625: Fix the interface instance
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The axi_ad9625_if does not have a DELAY_REFCLK_FREQUENCY parameter.
2019-06-13 10:59:43 +03:00
20b0c92a1f
iodelay: Expose the REFCLK_FREQUENCY parameter
2019-06-11 18:13:06 +03:00
c4c87c7c7a
axi_ad9361: Fix the _hw.tcl script
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This will fix an error introduced by 48d2c9d3
2019-06-11 12:39:20 +01:00
93b2254ff5
axi_ad9361: Fix for 'Define a MIMO enabled parameter'
2019-06-10 14:48:17 +01:00
48d2c9d36f
axi_ad9361: Define a MIMO enabled parameter
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Define a MIMO_ENABLE parameter for the core, which will insert
and additional de-skew logic to prevent timing issues coming from
the clock skew differences of two or multiple AD9361.
2019-06-10 15:16:47 +03:00
70b7d69ff8
whitespace: Delete all trailing white spaces
2019-06-07 10:20:15 +03:00
90f9b2c36a
avl_dacfifo: add missing constraint
2019-06-06 11:45:05 +03:00
4d966500a8
adi_ip_alt.tcl: Add comments to all proc
2019-05-31 10:32:40 +03:00
f2b3b7f493
adi_ip_alt.tcl: Delete deprecated procs
2019-05-31 10:32:40 +03:00
17afb4d9c5
adi_ip.tcl: Fix adi_add_multi_bus proc
...
The loop should iterate through the number of interfaces defined by the
$num attribute,
2019-05-31 10:32:40 +03:00
bd43b565ce
adi_ip.tcl: Add comments to all proc
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Add doxygen support for all proc. Description of the used layout can be
find at http://www.doxygen.nl/manual/docblocks.html#tclblocks
2019-05-31 10:32:40 +03:00
70d7840c2b
axi_fmcadc5_sync: define spi clock constraint
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Create the spi clock based on input clock for the worst case scenario.
2019-05-30 14:55:11 +03:00
87bb76934f
makefile: Update util_adcfifo
2019-05-29 10:23:24 +03:00
ba36c9cd57
makefile: Add axi_fan_control to library
2019-05-29 10:23:24 +03:00
3f7f2f9c9f
util_adcfifo: Fix the address generation and read logic
2019-05-28 08:48:16 +03:00
945d6910e7
axi_dmac: version bump for minor patches
2019-05-24 11:11:08 +03:00
ae027d467e
axi_dmac: clear measured transfer length when core disabled
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When core is disabled it clears all its status registers. The transfer length
register should not fall out from this rule.
2019-05-24 11:11:08 +03:00
01a2bab978
axi_dmac: fix transfer length reporting cyclic mode
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Let the measured transfer length to be cleared at the end of each
transfer, other case in cyclic mode the counter will overflow and will
not present any useful information.
2019-05-24 11:11:08 +03:00
42a7e87cb3
axi_dmac: patch xfer_request
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Once xfer_request is set the DMA must accept samples in the same clock
cycle if the fifo_wr_en signal is asserted.
If the req_valid asserts faster than the ID gets synchronized over the
the xfer request asserts without being ready to accept data.
This can lead to overflow assertion when using a FIFO like interface.
2019-05-24 11:11:08 +03:00
6fae37504b
axi_dmac: patch for partial transfers support
...
This patch addresses the following issue:
In case of transfers with multiple segments, if TLAST asserts on the last
beat of a non-last segment while more descriptors are queued up,
the completions for the queued segments may be missed causing timeout in
processes that wait for transfer completions.
2019-05-24 11:11:08 +03:00
5e1100ee77
axi_dmac: patch for partial 2D transfer support
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This patch addresses the following issue:
In 2D mode when consecutive partial transfers occur, and the latter is
very short, will interfere with the completion mechanism of the first
transfer leading to uncompleted segments and unreported partial
transfers.
2019-05-24 11:11:08 +03:00
a0d738e1a9
util_adxcvr: Add GTH parameters for line rate of 15Gbps
2019-05-24 11:05:36 +03:00
9832c87144
jesd204:tpl: add missing dependencies for Intel
2019-05-24 11:04:46 +03:00
157afcbc33
tb_base: Fix various test benches
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The tb_base.v verilog files does not contain a full module definition,
just some plain test code. In general the files is sourced inside the
test bench main module. As is, defining a timescale in these files will
generate an error, because timescale directive can not be inside a
module.
Delete all the timescale directive from these files.
2019-05-17 11:20:48 +03:00
b90c2e79dc
jesd204_rx: add parameter for input pipeline stages
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Pipeline stages must be implemented on register so placer can spread it
cross the device. Use the shreg_extract attribute to avoid SRL
inference.
2019-05-16 13:29:34 +03:00
96769c92bb
util_upack2: bundle AXIS signals into bus for Intel
2019-05-16 13:27:19 +03:00
9273cde33f
util_adcfifo/util_dacfifo: bundle AXIS signals into bus for Intel
2019-05-16 13:27:19 +03:00
eedb2ce0f4
avl_dacfifo: bundle AXIS signals into bus
2019-05-16 13:27:19 +03:00
dd952ddad1
axi_dmac: bundle AXI Stream signals into bus for Intel
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Add signals that are optional by standard but required by the
axi4stream interface definition. Make them selectable by parameters.
2019-05-16 13:27:19 +03:00
7f16f823ff
Revert "axi_dmac: add tlast to the axis interface for Intel"
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This reverts commit e2c75c015f
2019-05-16 13:27:19 +03:00
92d87c2d60
jesd204/scripts: fix indentation
2019-05-16 13:22:55 +03:00
cf258ace83
jesd204/scripts: TPL add support for M=1
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When only one converter is used there is no need for concatenation and
slicer cores. In that case the TPL will connect to port 0 from the
application layer.
2019-05-16 13:22:55 +03:00
168e1951ee
library: Add `timescale to modules that are missing it
2019-05-15 15:37:44 +03:00
f45408d6a9
util_adxcvr: Expose GTY4 parameters required for 15Gbps link
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These parameters must be overwritten when the link is at 15Gbps.
The parameters have a GTY4_ prefix since the same parameters are shared
between GTY4 and GTH4 having different default values.
2019-05-09 15:33:15 +03:00
572089657a
axi_dmac: infer interrupt line for Xilinx projects
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The interrupt controller from Microblaze based projects requires that
all its inputs have attributes which define the sensitivity of the
interrupt line. Other case it defaults to EDGE_RISING which is not the
case for DMAC, leading to incorrect interrupt reporting and handling in
case of such projects.
2019-04-25 08:25:02 +03:00
c32b4b02f3
sync_bits: Change I/O names of wires "in" and "out" for VHDL users
2019-04-23 18:03:23 +03:00
5b13e205b9
axi_mc_controller:axi_mc_current_monitor: define generated clocks in IP constraints file for better OOC integration
2019-04-22 10:27:16 +03:00
01748d4364
jesd204:axi_jesd204_tx: set OOC default clock constraints
2019-04-22 10:27:16 +03:00
4264a7a0dd
jesd204:axi_jesd204_rx: set OOC default clock constraints
2019-04-22 10:27:16 +03:00
0cc07a20c8
util_clkdiv: set OOC default clock constraints
2019-04-22 10:27:16 +03:00
e59e133663
util_dacfifo: set OOC default clock constraints
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Out of Context constraints are needed for timing driven synthesis as for
avoiding critical warnings due clock queries.
The memory from the FIFO is inferred in different ways for high clock
speeds. Assume the highest frequency for all projects.
2019-04-22 10:27:16 +03:00
dc78ee4982
axi_adc_decimate: fix dependencies
2019-04-22 10:27:16 +03:00
dcdcbc9378
Revert "axi_dmac: assert xfer_request only when ready"
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This reverts commit 9d6f3de448
2019-04-18 16:15:55 +03:00
c7098a9d49
axi_fan_control: Initial commit
2019-04-15 13:06:37 +03:00
Istvan Csomortani
Arpadi
Adrian Costina
AndreiGrozav
Laszlo Nagy