Lars-Peter Clausen
7d3be14ab5
common: Connect audio clkgen reset
...
While we are at it also hide the unused locked pin.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-15 18:44:46 +03:00
Lars-Peter Clausen
fd89458708
common: Set cpu interconnect strategy to minimize area
...
There will rarely be concurrent access to the peripheral control bus
interconnect, so there is no need to optimize for performace. Setting the
interconnect strategy to minimize area can reduce the resource usage by
~90%.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-15 18:43:54 +03:00
Istvan Csomortani
d2a04856a9
common: Fix xlconstant output pin name
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On 2014.2 xlconstant output pin name is 'dout'.
2014-10-15 15:37:06 +03:00
Michael Hennerich
cd42345324
projects/common/xxx/xxx_system_bd.tcl: 'Update microblaze defaults
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Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
2014-10-07 09:17:24 +02:00
Adrian Costina
041d8faaf7
common: Updated common projects for ac701/kc702/zc702/zed to vivado 2014.2
2014-09-30 10:31:00 +03:00
Lars-Peter Clausen
41cc92ef49
Remove BASEADDR/HIGHADDR parameters
...
This is unused and unneeded. The AXI interconnect will make sure that a
peripheral only gets requests that are meant for it, there is no need to
check the address in the peripheral itself.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-11 12:26:37 +02:00
Lars-Peter Clausen
50faf0c53a
Remove executable flags from non-exectuable files
2014-09-09 15:05:06 +02:00
Istvan Csomortani
fbafaa8507
MicroBlaze base system: Fix a few net names
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Every interconnect interface net name follows the convention:
<interconnect name>_<interface name>
No changes in logic or any connection!
2014-04-01 10:40:35 +03:00
Adrian Costina
a881557645
base_design: Fixed AC701 and VC707 contstraints
...
AC701: Modified the IOSTANDARD for some of the pins to correspond to the
AC701 user guide.
VC707: Fixed naming for some system clocks
2014-03-31 17:38:20 +03:00
Istvan Csomortani
0f10623be4
AC701/VC707: Define common variables
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Define variables sys_zynq, sys_mem_size, sys_addr_cntrl_space.
2014-03-25 14:24:51 +02:00
Istvan Csomortani
b94acf78aa
AC701 bases sys: Add an auxiliary cpu interconnect
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- Add an auxiliary cpu interconnect, the KC705 base system was
used as reference
- Base system is tested and working
2014-03-24 13:01:52 +02:00
Istvan Csomortani
8a08031dce
AC701: Modify interrupt concatenation
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- Interrupt concatenation is the same as in case of KC705
2014-03-24 10:20:56 +02:00
Istvan Csomortani
3a0d1282b7
Fix the remaining issues
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- Swap the IO locations of ports vsync and hsync
- Change the mem_interconnect optimization strategy to Maximize
Performance
2014-03-20 14:36:01 +02:00
Istvan Csomortani
7cdab9b5b0
Change the internal clock generator to Clock Wizard
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- Using a Clock Wizard Module, in place of the DDR Controler's MMCM for internal clock
generation.
2014-03-18 17:24:45 +02:00
Rejeesh Kutty
5c3b65d01b
adv7511: kc705/ac701 updates
2014-03-06 09:36:50 -05:00
Rejeesh Kutty
360f10395a
initial checkin
2014-03-03 13:42:25 -05:00