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16 Commits (dffbbfd7d1ab75c07877428789ae78086696b1e5)

Author SHA1 Message Date
Lars-Peter Clausen 8a487816b9 axi_ad6676: Use the generic JESD204 ADC receiver core 
Replace the axi_ad6676 implementation with the new generic JESD204
interface ADC core. The replacement is functionally equivalent, except that
the converter clock ratio is now correctly reported as 2 rather than 1 as
before.

Also the adc_rst output port is removed. It is not used in any design. The
current guidelines for the reset for the JESD204 subsystem is to use an
external reset generator.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2018-05-02 17:21:20 +02:00
Lars-Peter Clausen 324da5f112 Remove unused DMA underflow signal from ADC DMA interface 
The ADC DMA will never underflow and unsurprisingly the adc_dunf signal is
never used anywhere. It is very unlikely it will ever be used, so remove
it.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2018-05-02 17:21:20 +02:00
Lars-Peter Clausen 5b58fb67f0 library: Remove empty constraint files 
Most of the cores are fully covered by the generic constraint files. When
the constraints where moved from the core specific to the generic
constraint files some empty core constraints files where left around. These
don't do anything, so remove them.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2018-04-11 15:09:54 +03:00
Adrian Costina 74b922f9f8 axi_*: Infer clock and reset signals of an IP 
A clock sink must be connected to clock source, and a reset sink to
reset source, otherwise the tool will throw a synthesis warning.
By properly inferring all the reset and clock signals of an IP, we can
get rid of unwanted warning messages.

The following IPs tcl script was updated:
  - axi_ad9434
  - axi_hdmi_tx
  - util_cpack
  - util_adxcvr
  - axi_ad6676
  - axi_ad9625
  - axi_ad9379
  - axi_ad9265
  - util_tdd_sync
  - util_rfifo
  - util_wfifo
  - axi_ad9361
  - axi_ad9467
  - util_upack
  - axi_dacfifo
  - axi_ad9152
  - axi_ad9680
  - util_clkdiv
  - axi_ad9122
  - axi_ad9684
  - axi_mc_speed
  - axi_mc_current_monitor
  - axi_mc_controller
  - util_gmii_to_rgmii
  - util_adxcvr
  - axi_ad9379
  - axi_hdmi
  - library
  - axi_fmcadc5_sync
  - util_adcfifo
  - util_mfifo
  - axi_jesd204_rx
  - axi_jesd204_tx
  - axi_ad9361
  - axi_adxcvr_ip
 2018-04-11 15:09:54 +03:00
Istvan Csomortani c1bdfca4c3 library: Delete all adi_ip_constraint process call 2017-04-06 12:36:47 +03:00
Istvan Csomortani 873fbfd6d7 library: Update scripts with new constraints 
Update all IPs tcl scripts with the new constraints files.
Refer to commit 335fef0.
 2017-03-30 16:16:02 +03:00
Istvan Csomortani 8493bd4329 axi_ad6676: Update the core, sof interface added 2016-11-10 10:39:33 +02:00
Adrian Costina 37a4e976d6 axi_ad6676: Updated constraints 2015-09-25 17:02:42 +03:00
Istvan Csomortani 7b858bc5ad Revert commit 6b99ce 
Revert 6b99ce2482
 2015-08-26 13:48:28 +03:00
Adrian Costina 6b99ce2482 library: Added common constraints for all cores. Commented code that needs to be updated to 2015.2 2015-08-20 18:17:38 +03:00
Lars-Peter Clausen 6862655b0d Add .gitattributes file 
Add .gitattributes file which sets up the eol encoding handling. This will
make sure that we get a uniform eol encoding across different operating
systems.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2015-06-26 11:07:10 +02:00
Adrian Costina 8a1f4bf5f6 ad6676,ad9144,ad9152,ad9234,ad9250,ad9434,ad9467,ad9625,ad652,ad9671,ad9680,ad9739a:Set default driver value for overflow, underflow, gpio_in and dac_sync ports 2015-06-09 14:21:12 +03:00
Rejeesh Kutty 91b0f70972 library: remove drp cntrl 2015-06-02 09:58:57 -04:00
Rejeesh Kutty 0877c252ad delay-cntrl changes 2015-05-18 14:28:20 -04:00
Adrian Costina 691c54e0dd axi_ad6676: Added CDC and reset constraints 2015-04-23 10:16:29 +03:00
Rejeesh Kutty cb15567a56 ad6676: added 2014-11-10 13:36:07 -05:00