Commit Graph

5353 Commits (e00ee136f6017deec7acc8d80fc54df44ba409b7)

Author SHA1 Message Date
Istvan Csomortani bd43b565ce adi_ip.tcl: Add comments to all proc
Add doxygen support for all proc. Description of the used layout can be
find at http://www.doxygen.nl/manual/docblocks.html#tclblocks
2019-05-31 10:32:40 +03:00
Laszlo Nagy 08d01789c8 microblaze: add SPI clock constraint
The SPI clock is a generated clock from the system clock. Worst case
scenario is that the system clock is divided by two.
2019-05-30 14:55:11 +03:00
Laszlo Nagy 5986e87a1f zynq/zynqmp: create a 50MHz clock on the SPI clock outputs of the PS 2019-05-30 14:55:11 +03:00
Laszlo Nagy 70d7840c2b axi_fmcadc5_sync: define spi clock constraint
Create the spi clock based on input clock for the worst case scenario.
2019-05-30 14:55:11 +03:00
Laszlo Nagy 8390bf0ac6 adrv9361z7035:ccfmc_constr.xdc: constrain all input clocks 2019-05-30 14:55:11 +03:00
Laszlo Nagy aa0ea252ec fmcomms5: constrain ref clock 2019-05-30 14:55:11 +03:00
Laszlo Nagy 4fca24d41f vc707: define 125 MHz SGMII clock
Constrain the clock path to 125 MHz corresponding to the output of
ICS844021I which has a 25 MHz reference.
2019-05-30 14:55:11 +03:00
Istvan Csomortani e9a171df5f adi_board: Delete ad_reconct deprecated proc 2019-05-29 10:27:16 +03:00
Istvan Csomortani f113f8f32f ad9371x/common: Fix ad_xcvrcon proc call
The process ad_xcvrcon has a device_clk attribute which can be used to
connect a custom device clock to the XCVR. Fix the proc call so we can
simplify the block design script.
2019-05-29 10:27:16 +03:00
Istvan Csomortani 391ac468a7 adrv9009/common: Fix ad_xcvrcon proc call
The process ad_xcvrcon has a device_clk attribute which can be used to
connect a custom device clock to the XCVR. Fix the proc call so we can
simplify the block design script.
2019-05-29 10:27:16 +03:00
Istvan Csomortani 87bb76934f makefile: Update util_adcfifo 2019-05-29 10:23:24 +03:00
Istvan Csomortani c1bfd9ddab makefile: Update fmcomms11 2019-05-29 10:23:24 +03:00
Istvan Csomortani 6cac0b9917 makefile: Update dual_ad9208 2019-05-29 10:23:24 +03:00
Istvan Csomortani ba36c9cd57 makefile: Add axi_fan_control to library 2019-05-29 10:23:24 +03:00
Istvan Csomortani 3f7f2f9c9f util_adcfifo: Fix the address generation and read logic 2019-05-28 08:48:16 +03:00
AndreiGrozav 4aa3e94089 pluto: Fix the adc/dac dma mapping to ps7 S_AXI_HP1/S_AXI_HP2
After the previous commit that removed the interconnects from HP ports
in order to reduce utilization. The directly connected DMAs were not
assigned to a specific range and address.
2019-05-27 17:20:44 +03:00
Istvan Csomortani 3adefaddfd adi_xilinx_msg: New updates for 2018.3 2019-05-27 16:58:34 +03:00
AndreiGrozav 958ba7c3af common zed, zc702 and zc706: Remove parameter assignment
The SYNC_TRANSFER_START parameter is disabled in this configuration
of the axi_dmac, trying to set the parameter will generate a warning.
2019-05-27 16:48:26 +03:00
Laszlo Nagy ab7ab3b32f scripts/adi_project.tcl: make search for undefined clocks more robust
Since we parse the output of a command it is likely to break in the
future if the format of the sting changes. Create a warning for that case.
2019-05-24 13:38:01 +03:00
Laszlo Nagy 945d6910e7 axi_dmac: version bump for minor patches 2019-05-24 11:11:08 +03:00
Laszlo Nagy ae027d467e axi_dmac: clear measured transfer length when core disabled
When core is disabled it clears all its status registers. The transfer length
register should not fall out from this rule.
2019-05-24 11:11:08 +03:00
Laszlo Nagy 01a2bab978 axi_dmac: fix transfer length reporting cyclic mode
Let the measured transfer length to be cleared at the end of each
transfer, other case in cyclic mode the counter will overflow and will
not present any useful information.
2019-05-24 11:11:08 +03:00
Laszlo Nagy 42a7e87cb3 axi_dmac: patch xfer_request
Once xfer_request is set the DMA must accept samples in the same clock
cycle if the fifo_wr_en signal is asserted.

If the req_valid asserts faster than the ID gets synchronized over the
the xfer request asserts without being ready to accept data.
This can lead to overflow assertion when using a FIFO like interface.
2019-05-24 11:11:08 +03:00
Laszlo Nagy 6fae37504b axi_dmac: patch for partial transfers support
This patch addresses the following issue:

  In case of transfers with multiple segments, if TLAST asserts on the last
beat of a non-last segment while more descriptors are queued up,
the completions for the queued segments may be missed causing timeout in
processes that wait for transfer completions.
2019-05-24 11:11:08 +03:00
Laszlo Nagy 5e1100ee77 axi_dmac: patch for partial 2D transfer support
This patch addresses the following issue:

  In 2D mode when consecutive partial transfers occur, and the latter is
very short, will interfere with the completion mechanism of the first
transfer leading to uncompleted segments and unreported partial
transfers.
2019-05-24 11:11:08 +03:00
Istvan Csomortani 68a5f2f86c fmcomms11: Add a upack module into the TX path
Because the AD9162 will run in M=2 mode, we have to put a upack module
between the TPL and FIFO/DMA.
2019-05-24 11:07:13 +03:00
Adrian Costina a0d738e1a9 util_adxcvr: Add GTH parameters for line rate of 15Gbps 2019-05-24 11:05:36 +03:00
Laszlo Nagy bf31f949e6 scripts/adi_project:adi_project_alt: add parameters to top level
Allow the top level files to have parameters.
Pass the parameters from system_project.tcl to the Vivado/Quartus project and
to the block design scripts through ad_project_params variable.

Usage:

1. create a project with a list of parameters:

adi_project_xilinx  my_project [list PARAM_A PARAM_A_VALUE PARAM_B PARAM_B_VALUE]
or
adi_project_altera  my_project [list PARAM_A PARAM_A_VALUE PARAM_B PARAM_B_VALUE]

2. access the parameter in QSYS or block design through the $ad_project_params variable

e.g
  set PARAM_A $ad_project_params(PARAM_A)
  set PARAM_B $ad_project_params(PARAM_B)

3. In system_top.v use PARAM_A and PARAM_B as parameters/generics
2019-05-24 11:05:10 +03:00
Laszlo Nagy 9832c87144 jesd204:tpl: add missing dependencies for Intel 2019-05-24 11:04:46 +03:00
Robin Getz 5794b67fe0 Update README.md
Promote support, and add a few more details.
2019-05-22 11:04:06 +03:00
Istvan Csomortani 157afcbc33 tb_base: Fix various test benches
The tb_base.v verilog files does not contain a full module definition,
just some plain test code. In general the files is sourced inside the
test bench main module. As is, defining a timescale in these files will
generate an error, because timescale directive can not be inside a
module.

Delete all the timescale directive from these files.
2019-05-17 11:20:48 +03:00
Adrian Costina 1c8e71ec4e fmcadc4: Remove project 2019-05-16 15:10:04 +01:00
Laszlo Nagy ec636b785a scripts:adi_project.tcl: add check for missing clock definitions
Look for undefined clocks which do not show up in the timing summary
therefore can lead to silent failures.
If clocks are not defined they are not analyzed during the timing
checks.
2019-05-16 14:55:35 +03:00
Laszlo Nagy 607f2bd8de ad9208_dual_ebz: Initial version
This commit add support for the dual AD9208-DUAL-EBZ board.

The clocking scheme is different from the other projects.
The device clock (LaneRate/40) is no longer an output of the transceivers (RXOUTCLOCK),
it is received directly from the clockchip  SCLKOUT9 output through the REFCLK1.
This is needed for deterministic latency where SYSREF must be sampled
with the device clock by meeting setup and hold time.

The two channels from each converter are merged together and transferred  to the DDR with a single DMA.

It has all transceiver parameters set for a 15Gpbs lane rate and uses the QPLL.

REQUIRED HARDWARE CHANGES : The F1 2A fuse must be populated on the FMC
board.
2019-05-16 13:29:34 +03:00
Laszlo Nagy b90c2e79dc jesd204_rx: add parameter for input pipeline stages
Pipeline stages must be implemented on register so placer can spread it
cross the device. Use the shreg_extract attribute to avoid SRL
inference.
2019-05-16 13:29:34 +03:00
Laszlo Nagy 6c6d14722d daq3:qsys: use bundled AXIS interface 2019-05-16 13:27:19 +03:00
Laszlo Nagy 089cd882bc daq2:qsys: use bundled AXIS interface 2019-05-16 13:27:19 +03:00
Laszlo Nagy fd88906b6b aradio:qsys: use bundled AXIS interface 2019-05-16 13:27:19 +03:00
Laszlo Nagy 7afc9e77a2 adrv9371:qsys: use bundled AXIS interface 2019-05-16 13:27:19 +03:00
Laszlo Nagy c930395773 adrv9009:qsys: use bundled AXIS interface 2019-05-16 13:27:19 +03:00
Laszlo Nagy 96769c92bb util_upack2: bundle AXIS signals into bus for Intel 2019-05-16 13:27:19 +03:00
Laszlo Nagy 9273cde33f util_adcfifo/util_dacfifo: bundle AXIS signals into bus for Intel 2019-05-16 13:27:19 +03:00
Laszlo Nagy eedb2ce0f4 avl_dacfifo: bundle AXIS signals into bus 2019-05-16 13:27:19 +03:00
Laszlo Nagy dd952ddad1 axi_dmac: bundle AXI Stream signals into bus for Intel
Add signals that are optional by standard but required by the
axi4stream interface definition. Make them selectable by parameters.
2019-05-16 13:27:19 +03:00
Laszlo Nagy 7f16f823ff Revert "axi_dmac: add tlast to the axis interface for Intel"
This reverts commit e2c75c015f.
2019-05-16 13:27:19 +03:00
Istvan Csomortani 7b26190716 fmcomms11: By default we support complex mode 2019-05-16 13:26:58 +03:00
Istvan Csomortani cf03e216fe fmcomms11: Update the project with the new TPL 2019-05-16 13:26:58 +03:00
Istvan Csomortani eba1975144 fmcomms11: Initial commit 2019-05-16 13:26:58 +03:00
Laszlo Nagy 92d87c2d60 jesd204/scripts: fix indentation 2019-05-16 13:22:55 +03:00
Laszlo Nagy cf258ace83 jesd204/scripts: TPL add support for M=1
When only one converter is used there is no need for concatenation and
slicer cores. In that case the TPL will connect to port 0 from the
application layer.
2019-05-16 13:22:55 +03:00