zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
2,512 Commits
1 Branch
0 Tags
23 MiB
Commit Graph

1496 Commits (e012d0519baf415f36e6956113c5b60feb28e619)

Author SHA1 Message Date
Rejeesh Kutty e012d0519b Merge remote-tracking branch 'origin/hdl_2015_r2' into dev 2016-02-26 13:39:39 -05:00
Rejeesh Kutty f6e64e42b0 kcu105: add ethernet idelaycntrl 2016-02-26 13:19:49 -05:00
Istvan Csomortani 59313f3c90 daq1: ADC DMA must be in none-cyclic mode 2016-02-24 14:37:19 +02:00
Istvan Csomortani c0a559a9b1 daq1: Fix some typos in the SPI wrapper 2016-02-24 14:31:56 +02:00
Adrian Costina 8ccd8d87bb daq2: A10GX, increase analog/digital reset durations 
- reset the xcvr_rst_cntrl only from the axi_jesd_xcvr
- checked separate RX/TX reset per channel
 2016-02-23 11:41:38 +02:00
Adrian Costina 89f7aadfb1 fmcjesdadc1: A5GT, connected xcvr_rxt_cntrl reset input to the axi_jesd_xcvr reset output 
This will allow for the transceivers to be reset by the axi_jesd_xcvr core
 2016-02-23 11:31:07 +02:00
Rejeesh Kutty 4fb6589b2d pzsdr/ccfmc: add fan controls 2016-02-19 16:40:54 -05:00
Adrian Costina 377461e0d4 Merge branch 'hdl_2015_r2' into dev 2016-02-19 14:15:27 +02:00
Adrian Costina 0f37dd6424 fmcjesdadc1: Fixed project 
- changed system_project.tcl so that all base designs to be included
- changed DMA properties to take into consideration the new parameter names
- changed reset bridges to asynchronous
- increased maximum burst size of the DMA bridge
- changed the data_width of the memory bus to 256, as with 512 timing violations may occur
- changed base addresses for the base system to be the same as in the previous release
 2016-02-19 14:09:57 +02:00
Rejeesh Kutty ce760eb691 fmcadc2- add adf4355 access 2016-02-18 16:17:33 -05:00
Adrian Costina d94f157454 arradio: Changed ADC/DAC DMA address length to 24 bit 2016-02-16 15:27:51 +02:00
Adrian Costina 43e03ca6f7 arradio: Updated project 
- made the reset bridges asynchronous
- connected the arradio gpio to the CPU interconnect
 2016-02-16 14:50:23 +02:00
Istvan Csomortani 5518c47ca4 daq1_cpld: Set Input and tristate I/O termination mode to FLOAT 2016-02-15 19:27:59 +02:00
Istvan Csomortani 051ac307e6 daq1_cpld: Do not forward the first eight clock cycles of fmc_spi_sclk to sclk 2016-02-15 19:26:58 +02:00
Istvan Csomortani 9370246cfa daq1: Fix bugs on CPLD design 
Fix the CSN forwarding.
 2016-02-12 16:59:09 +02:00
Istvan Csomortani 5ed2c0b599 daq1: Update CPLD constraints file 2016-02-12 16:54:36 +02:00
Istvan Csomortani aa2ff0223a daq1: Update CPLD design 
+ SPI counter counts on negative edge of the SPI_CLK
+ Shift register for read, shifting MSB first
+ Fix write access logic
+ Update the internal register addresses
 2016-02-12 14:45:18 +02:00
Istvan Csomortani c32d7147d5 daq1 : There is a single CSN from master 2016-02-12 14:38:32 +02:00
Istvan Csomortani 9675df15c6 daq1_zc706: Update constraints file 2016-02-12 14:37:02 +02:00
Istvan Csomortani e381d5170c util_tdd_sync: Update the synchronization interface 
Simplify the synchronization interface, there is one signal line between the synchronization module and transceiver core.
 2016-02-12 14:27:37 +02:00
Adrian Costina 61f9f72a75 fmcjesdadc1: Updated VC707 project for maximum throughput from DMA to DDR 
- Increased the DMAs internal FIFO
 2016-02-09 12:30:56 +02:00
Adrian Costina c431adb793 fmcjesdadc1: Updated KC705 project for maximum throughput from DMA to DDR 
- Increased the DMA internal FIFO
 2016-02-09 12:00:27 +02:00
Adrian Costina ad9ecbbbb6 daq2: Updated a10gx project to quartus 15.1.1 2016-02-05 17:43:05 +02:00
Rejeesh Kutty bb62f6d225 pzsdr1- updates 2016-02-02 12:34:09 -05:00
Rejeesh Kutty 41b6ebeeaf pzsdr1- updates 2016-02-02 12:33:55 -05:00
Rejeesh Kutty b147e9c94a pzsdr1- updates 2016-02-02 12:33:01 -05:00
Rejeesh Kutty 170295161f pzsdr1- xdc 2016-01-26 11:19:00 -05:00
Rejeesh Kutty bcac3eef4d pzsdr1- initial commit 2016-01-25 16:07:33 -05:00
Rejeesh Kutty 44a382fc69 pzsdr1-added 2016-01-25 15:33:34 -05:00
Istvan Csomortani e22d5d5c18 daq2: Fix clock constraints for KC705 and VC707 2016-01-22 19:09:57 +02:00
Adrian Costina 59fbd99fdb fmcjesdadc1: Added clock constraint for the ADC path 2016-01-22 15:46:20 +02:00
Adrian Costina dca39c26f9 ad6676evb: Added clock constraint for the ADC path 2016-01-22 15:45:16 +02:00
Adrian Costina 9cd0378003 fmcadc2: Added clock constraint for the ADC path 2016-01-22 15:44:04 +02:00
Istvan Csomortani aa77af6bdf daq1_cpld: Add ISE project file 
This file, along with the project source files, is sufficient to open and implement in ISE Project Navigator.
 2016-01-21 18:05:59 +02:00
Istvan Csomortani 8c69c9d2ce daq1_zc706 : Update the project 
+ Add AD9684 to the block design
+ Update the IO definitions
+ Update the CPLD design
+ Add 3wire SPI logic
 2016-01-19 11:20:35 +02:00
István Csomortáni ab99c4456a ad9434_fmc: Delete unnecessary set_property call 
HPx interface is activated by the ad_mem_hpx_interconnect process
 2016-01-14 15:41:23 +02:00
Lars-Peter Clausen c094ab8b52 cn0363: Add support for the MicroZed 
Add support for connecting the CN0363 to the MicroZed. This works in
combination with the MicroZed Arduino carrier board. The CN0363 needs to be
connected to the PLPMOD header.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2016-01-13 20:32:26 +01:00
Lars-Peter Clausen 514eb68876 cn0363: Factor out common parts 
Factor out the common parts of the cn0363 design so we can use it to add
support for other carriers.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2016-01-13 20:32:26 +01:00
Lars-Peter Clausen d2b26720e6 common: microzed: Add clock, reset and interrupt support 
In order for the base project to be usable by other projects it needs to
create the clock, reset and interrupt signals that are expected to exist.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2016-01-13 20:32:26 +01:00
Lars-Peter Clausen 51d20b1a61 adi_project.tcl: Add MicroZed support 
Handle the projects for the MicroZed and set up the FPGA part accordingly.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2016-01-13 20:32:26 +01:00
Lars-Peter Clausen 426490c394 common: Rename uzed to microzed 
Everybody calls the MicroZed microzed in their projects. Don't deviate from
that to avoid potential confusion.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2016-01-13 20:18:57 +01:00
Rejeesh Kutty c397787001 uzed: updates 2016-01-11 15:36:01 -05:00
Rejeesh Kutty a610ebb413 uzed: zed-copy 2016-01-11 13:53:22 -05:00
Istvan Csomortani 02cc926275 daq1: Add CPLD logic and IO constraints 2016-01-04 18:10:46 +02:00
Adrian Costina 7013b319b0 motcon2_fmc: Fixed reset connection for cpack cores 2015-12-22 12:03:34 +02:00
Rejeesh Kutty 2bb19be3d3 pzsdr/ccfmc: sfp io control 2015-12-17 16:18:06 -05:00
Rejeesh Kutty f3fe16a102 pzsdr/ccfmc: camera/sfp pin changes 2015-12-17 16:17:24 -05:00
Rejeesh Kutty ea045a3f9a fmcadc4: change qpll to receive 2015-12-17 12:34:47 -05:00
Rejeesh Kutty 40ab2f5e6a ccfmc: tdd/gpio bit moved to the top 2015-12-17 11:37:57 -05:00
Adrian Costina 34b832e22a fmcomms6: Fixed reset connection for cpack core 2015-12-16 10:36:33 +02:00