13 Commits (e012d0519baf415f36e6956113c5b60feb28e619)

Author	SHA1	Message	Date
Adrian Costina	0f37dd6424	fmcjesdadc1: Fixed project ... - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release	2016-02-19 14:09:57 +02:00
Adrian Costina	fd3910a915	fmcjesdadc1: Updated a5gt design	2015-11-24 15:39:21 +02:00
Rejeesh Kutty	3ccf1bef36	base system modifications	2015-07-23 15:23:10 -04:00
Rejeesh Kutty	a454b73d27	fmcjesdadc1/a5gt: split xcvr cores	2015-07-15 09:44:53 -04:00
Rejeesh Kutty	f64df40a0a	signal tap removed	2015-07-08 15:47:50 -04:00
Rejeesh Kutty	18e8914087	fmcjesdadc1/a5gt: pn-errors version	2015-07-01 13:43:12 -04:00
Rejeesh Kutty	15740a7d34	fmcjesdadc1- 15.0 updates	2015-06-24 05:31:09 -04:00
Rejeesh Kutty	cb29b83b05	a5gt: updates to match a5gt	2014-08-25 10:46:59 -04:00
Rejeesh Kutty	6a19b34a00	a5gt: added tightly coupled memory	2014-04-03 20:50:17 -04:00
Rejeesh Kutty	12e5cc91bd	make signaltap/timing part of the flow	2014-04-03 20:50:15 -04:00
Rejeesh Kutty	e85153b5dd	altera hal version	2014-04-01 21:12:11 -04:00
Rejeesh Kutty	04df908fbf	altera-fmcjesdadc1 initial checkin	2014-04-01 12:01:57 -04:00
Rejeesh Kutty	0d678b89ed	altera a5gt fmcjesdadc1 setup	2014-04-01 11:46:37 -04:00