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95 Commits (e23121fe3898be98aea3faf734db251bf46ec2ce)

Author SHA1 Message Date
Istvan Csomortani d5d305ec79 fmcadc2: Fix connection between a db port and a net 
The block design port should always be the first argument of the
ad_connect process call.
 2017-08-07 17:00:01 +03:00
Rejeesh Kutty 0aafd049c9 hdlmake.pl- remove ad_lvds 2017-07-26 10:32:44 -04:00
Rejeesh Kutty 893af8d3e6 library & projects- ad_lvds/ad_data replace 2017-07-26 10:31:48 -04:00
Lars-Peter Clausen 0360e8587e Connect JESD204 interrupts 
Connect the ADI JESD204 link layer peripheral interrupt signals in all
projects.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2017-07-05 14:37:50 +02:00
Adrian Costina b7ca17f02b scripts: Change adi_project_create to adi_project_xilinx for creating xilinx projects 2017-06-07 12:06:50 +03:00
Istvan Csomortani 50cdb6db67 Merge branch 'jesd204' into dev 2017-05-31 20:44:32 +03:00
Istvan Csomortani 84b2ad51e2 license: Add some clarification to the header license 2017-05-31 18:18:56 +03:00
Istvan Csomortani 85ebd3ca01 license: Update license terms in hdl source files 
Fix a few gramatical error, fix the path of the top level license
files.
 2017-05-29 09:55:41 +03:00
Lars-Peter Clausen bbe457acea fmcadc2: Convert to ADI JESD204 
Convert the FMCADC2 project to the ADI JESD204 link layer core. The change
is very straight forward, but a matching change on the software side is
required.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2017-05-23 11:16:07 +02:00
Rejeesh Kutty 0eaa98370e fmcadc2/vc707- spi clock reg can't be on iob 2017-05-19 15:22:33 -04:00
Istvan Csomortani 9055774795 all: Update license for all hdl source files 
All the hdl (verilog and vhdl) source files were updated. If a file did not
have any license, it was added into it. Files, which were generated by
a tool (like Matlab) or were took over from other source (like opencores.org),
were unchanged.

New license looks as follows:

Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.

Each core or library found in this collection may have its own licensing terms.
The user should keep this in in mind while exploring these cores.

Redistribution and use in source and binary forms,
with or without modification of this file, are permitted under the terms of either
 (at the option of the user):

  1. The GNU General Public License version 2 as published by the
     Free Software Foundation, which can be found in the top level directory, or at:
https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html

OR

  2.  An ADI specific BSD license as noted in the top level directory, or on-line at:
https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
 2017-05-17 11:52:08 +03:00
Istvan Csomortani 0442e7d404 util_adxcvr: Fix parameter setup at instantiation 
If a parameter value is defined as a string binary (e.g. "001001000000"),
it can confuse the tool, and the value may be used as a decimal number.
To prevent this issue and to improve readability converting all the binary
constants into hexadecimal.
 2017-04-27 15:35:39 +03:00
Istvan Csomortani 1c23cf4621 all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
AndreiGrozav 04a4001dba Ip automatic version update: fmcadc2, fmcadc5 2017-04-12 19:03:16 +03:00
Rejeesh Kutty 8063ba2b66 make updates 2017-03-20 16:05:18 -04:00
Rejeesh Kutty fb4a583613 projects/system_bd- adc/dac fifo board designs 2017-02-27 16:06:39 -05:00
Istvan Csomortani ac2e5a9dac constraints: Update constraints 
Xilinx recommends that all synchronizer flip-flops have
their ASYNC_REG property set to true in order to preserve the
synchronizer cells through any logic optimization during synthesis
and implementation.
 2017-02-24 13:43:32 +02:00
Rejeesh Kutty edd5e9570f file renamed; sed output; fingers crossed 2017-02-22 15:56:37 -05:00
Istvan Csomortani 343d0472d4 fmcadc2: Move GT setting to common/system_bd.tcl 2017-02-16 14:56:25 +02:00
Istvan Csomortani 07184b31d2 fmcadc2: Define default clock selection for Xilinx GTs 2017-02-16 12:35:24 +02:00
Istvan Csomortani 1156aeac16 ad_sysref_gen: Update SYSREF related constraints 2016-12-19 18:07:05 +02:00
Istvan Csomortani 0c42e04bc3 fmcadc2: Integrate ad_sysref_gen into the project 2016-12-19 12:16:05 +00:00
AndreiGrozav c455d2d64f fmcadc2/vc707: Disabele axi_spi constraint file 
The interface ports of the AXI SPI IP are not connected
  directly to a IOBUF, this results in a CRITICAL WARNING
 2016-12-13 19:15:44 +02:00
Adrian Costina 8ebc8fe4e2 updated makefiles 2016-12-09 23:06:41 +02:00
AndreiGrozav 3dceb53984 fmcadc2/vc707: Fix timing violations 2016-12-08 19:51:18 +02:00
AndreiGrozav 8eaae98728 fmcadc2: Updates 2016-12-07 21:43:19 +02:00
Rejeesh Kutty 170c781d02 hdlmake.pl- updates 2016-12-01 13:52:11 -05:00
Rejeesh Kutty daa3df4b96 projects/- xcvr updates 2016-11-22 16:23:05 -05:00
AndreiGrozav aff45eae5f fmcadc2: xcvr updates 2016-11-21 18:45:38 +02:00
Istvan Csomortani 16ee1336c3 Makefile: Update make files 2016-09-15 11:41:06 +03:00
AndreiGrozav 93fa5aeec3 fmcadc2/vc707: Add adf4355 access, update design to Vivado 2016.2 2016-09-01 16:11:39 +03:00
AndreiGrozav 2015bcedaa fmcadc2: Update common design to Vivado 2016.2 2016-08-30 16:42:58 +03:00
Rejeesh Kutty ce1fed1ce6 dmafifo- adc/dac split 2016-08-16 12:54:39 -04:00
Istvan Csomortani 0cd608a7e2 lib_refactoring: Update Make files 2016-08-08 16:38:38 +03:00
Istvan Csomortani df36902713 lib_refactoring: Fix path of the IO macros 2016-08-08 15:07:19 +03:00
Adrian Costina d60bce654c Makefiles: Updated Makefiles so they run correctly with gnuwin32 tools 2016-08-05 15:16:04 +03:00
Rejeesh Kutty e42b4ea378 hdlmake- updates 2016-08-04 13:28:25 -04:00
Istvan Csomortani 7ca8e10004 make: Update Make files 2016-08-01 14:24:48 +03:00
Istvan Csomortani b0538a03a2 Make: Update 2016-05-06 16:44:24 +03:00
Istvan Csomortani 4863a04132 axi_adc/dacfifo: Split the intergration script file 
Split the integration script file into two separate script files. Rename the
integration processes names to be more meaningful.
 2016-05-05 09:53:55 +03:00
AndreiGrozav be74db656c ad6674evb, fmcadc2, fmcadc4, fmcadc5, fmcjesdadc1: 
Update system_project.tcl scripts to correctly select the necessary
constraint files
 2016-05-04 19:37:33 +03:00
AndreiGrozav 3ca3414522 fmcadc2: Fixed bus data width 2016-05-04 19:20:01 +03:00
AndreiGrozav 9104b2cc60 ad6676evb, fmcadc2, fmcadc4, fmcadc5,... 
ad6676evb, fmcadc2, fmcadc4, fmcadc5, fmcjesdadc1: Remove unused
set_proprieties
 2016-05-04 19:13:25 +03:00
Rejeesh Kutty 385ed31a45 make files update 2016-04-29 10:17:35 -04:00
AndreiGrozav 679d471d75 Merge branch 'hdl_2016_r1' into dev 
hdl_2016_r1 contains IP core upgrades to Vivado 2015.4.2 and hdmi_tx improvements.
 2016-04-19 18:05:50 +03:00
Rejeesh Kutty 3006c5a223 make updates 2016-04-11 16:14:59 -04:00
AndreiGrozav 21208ca208 Makefiles: Update Makefiles 2016-03-31 12:37:47 +03:00
AndreiGrozav 98cc7dad7d fmcadc2: Updated common design to 2015.4 2016-03-15 15:26:05 +02:00
Adrian Costina 977d9d0624 Merge branch 'hdl_2015_r2' into dev 
Conflicts:
	projects/daq1/common/daq1_spi.v
 2016-03-02 13:52:15 +02:00
Adrian Costina 40fb68dfd5 ad9265, ad9434, ad9467, daq1, daq2, daq3, fmcadc2, fmcadc4, fmcadc5, fmcjesdadc1, fmcomms6, fmcomms7, usdrx1: updated common spi module so that spi streaming is possible 2016-03-02 13:39:37 +02:00