Istvan Csomortani
|
fa5f81f6c6
|
axi_dacfifo: Fix clock for read address generation
|
2017-04-03 10:39:17 +03:00 |
|
Istvan Csomortani
|
7cb7bc111e
|
axi_dacfifo: Delete unused wires
|
2017-04-03 10:38:50 +03:00 |
|
Istvan Csomortani
|
14b4c4cf5f
|
axi_dacfifo: Define constraint for bypass
The bypass module currently is supported, when the DMA data width
is equal with the DAC data width.
The dac_data output is enabled with dac_valid.
|
2017-04-03 10:38:28 +03:00 |
|
Istvan Csomortani
|
06605ed1e1
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axi_dacfifo: Register the dac_valid signals
|
2017-04-03 10:38:09 +03:00 |
|
Istvan Csomortani
|
77081a6233
|
axi_dacfifo: Data from DMA is validated with dma_ready too
|
2017-04-03 10:37:45 +03:00 |
|
Istvan Csomortani
|
af3a4f5fc9
|
axi_dacfifo: axi_dvalid should come from dacfifo_rd module
|
2017-04-03 10:37:30 +03:00 |
|
Istvan Csomortani
|
b30041f7f3
|
axi_dacfifo: Redesign the bypass functionality
|
2017-04-03 10:37:08 +03:00 |
|
Istvan Csomortani
|
434d1ea52c
|
axi_dacfifo: Fix constraints
|
2017-04-03 10:36:46 +03:00 |
|
Istvan Csomortani
|
981a61bf16
|
axi_dacfifo: Clean up the axi_dacfifo_wr.v module
|
2017-02-17 18:40:02 +02:00 |
|
Istvan Csomortani
|
f10866e4c3
|
axi_*fifo: Delete/replace AXI_BYTE_WIDTH parameter
|
2017-02-16 19:54:41 +02:00 |
|
Istvan Csomortani
|
95a4ea20c8
|
axi_dacfifo: Delete redundant parameter BYPASS_EN
|
2017-02-16 19:53:44 +02:00 |
Adrian Costina
|
8ebc8fe4e2
|
updated makefiles
|
2016-12-09 23:06:41 +02:00 |
Rejeesh Kutty
|
9defccef70
|
dacfifo- axi address map fixes
|
2016-09-27 14:48:23 -04:00 |
|
Istvan Csomortani
|
3b0c1e02fc
|
axi_dacfifo: Move IP to library/xilinx
|
2016-09-15 11:38:16 +03:00 |