db459d96e9
daq2: zc706: Increase DAC FIFO size
...
Currently the DAC FIFO size for the ZC706 DAQ2 project is 16kB. This is
quite a limiting size for practical applications. Increase the size to 1MB
to allow loading larger waveforms.
In this configuration the DAC FIFO will use half of the available BRAM
cells in the FPGA. This still leaves quite a few BRAMs available for
user application logic added to the design. If a user design should run out
of BRAMs nevertheless they can reduce the FIFO size, if not required by the
application, to free up some cells.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-28 11:34:45 +02:00
01165c926c
ad6676evb: Set default xcvr parameters to common design
2017-04-18 11:26:51 +03:00
7c191a089f
fmcjesdadc1: Update xcvr configuration to the default one used for this board
2017-04-12 14:41:43 +03:00
b30041f7f3
axi_dacfifo: Redesign the bypass functionality
2017-04-03 10:37:08 +03:00
040b61de60
fmcadc5: Updated default parameters
2017-02-20 17:13:58 +02:00
a15e05c497
adcfifo- remove axi-byte-width parameter
2017-02-17 15:29:10 -05:00
cb3d1883bc
fmcjesdadc1/a5gt- hard placement of ddr hr/qr registers
2017-02-17 15:21:33 -05:00
e8bcbb74da
scripts: fixed tcl syntax for altera projects not meeting timing
2017-02-16 21:21:51 +02:00
95a4ea20c8
axi_dacfifo: Delete redundant parameter BYPASS_EN
2017-02-16 19:53:44 +02:00
8453d758c2
scripts: If an altera project doesn't meet timing, rename the sof
2017-02-16 19:20:49 +02:00
343d0472d4
fmcadc2: Move GT setting to common/system_bd.tcl
2017-02-16 14:56:25 +02:00
07184b31d2
fmcadc2: Define default clock selection for Xilinx GTs
2017-02-16 12:35:24 +02:00
86c279c238
pzsdr1: ccbox, moved I2S core to DMA0 and DMA1 to fix critical warnings
2017-02-14 14:51:49 +02:00
46290193f3
pzsdr2: ccusb, renamed clk_out to clkout_in
2017-02-14 11:58:11 +02:00
27119343f2
pzsdr2: ccusb, connect unused clock pins to GND
2017-02-14 11:56:54 +02:00
fa37f4dd0a
pzsdr2: Don't set a disabled parameter
2017-02-14 11:56:08 +02:00
6a9b7580de
pzsdr1: ccusb, renamed clk_out to clkout_in
2017-02-14 11:54:46 +02:00
acef0113d1
pzsdr1: ccusb, connect unused clock pins to GND
2017-02-14 11:50:37 +02:00
46883731eb
pzsdr1: Don't set a disabled parameter
2017-02-14 11:50:06 +02:00
a569b6bf0c
pluto: Interpolation, connect fifo_rd_valid to s_axis_data_tvalid
2017-02-13 18:08:52 +02:00
e215a091b2
m2k: standalone, added explicit fclk_clk0 and fclk_clk1 constraints
2017-02-13 12:02:59 +02:00
4e62fb0ef3
m2k: Add reset circuitry on the logic_analyzer clock domain
2017-02-13 12:02:11 +02:00
5fa6dba333
Make: Update Makefiles
2017-02-10 16:32:58 +02:00
f5f1f47691
ad9467_fmc: Delete asynchronous clock group definition
...
This is a very bad way to handle timing. All the false path
should be defined explicitly, rather than define asynchronous clock
domains.
2017-02-10 16:21:35 +02:00
c39ed08edd
zcu102/*- actual clock == desired clock
2017-02-06 12:53:47 -05:00
58872aa3ef
fmcomms2/zc706pr- prcfg is a single clock synchronous design
2017-02-06 10:59:18 -05:00
971bcbb0fc
fmcomms1: Remove project
2017-02-03 16:42:44 +02:00
096274a033
daq2/zcu102- fix refclock pin swap
2017-02-03 09:26:07 -05:00
7c363cd5a7
daq3/a10gx/system_constr.sdc- fix typo
2017-02-03 09:26:07 -05:00
35f660fe06
fmcjesdadc1/vc707- constraint clean-up
2017-02-02 15:05:49 -05:00
d46352928a
fmcomms5- fix ovf net connections
2017-02-02 14:24:06 -05:00
6aadb49e80
m2k: Remove use board flow from the standalone version
2017-02-02 12:58:58 +02:00
0d0c3e99fd
m2k: Added I2C pull-ul, removed SLEW constraints
2017-02-02 12:35:46 +02:00
85ff496c12
daq2/a10gx- gpio match with others
2017-02-01 20:54:56 -05:00
5155b3f46d
m2k: Fix gpio buswidth
2017-02-01 17:43:01 +02:00
cfff70d358
M2K: Update standalone project
...
- configured PS7 similar to pluto. Added specific constraints instead of default PS7
- moved ad9963_resetn and en_power_analog to gpio[0] and gpio[1]
2017-02-01 14:27:11 +02:00
6bdd853b88
m2k: Updated PS7 configuration
2017-01-31 23:08:53 +02:00
b14d740f87
M2K: initial commit
2017-01-31 16:43:40 +02:00
d5af828b9c
Merge branch 'dev' into hdl_2016_r2
2017-01-30 17:10:05 +02:00
97d72d2f65
a10gx- xilinx/altera sync-up
2017-01-30 10:01:28 -05:00
b14e7fe4ee
daq3/kcu105- 1.25GSPS
2017-01-30 10:01:28 -05:00
48ad24cdbe
enable partial reconfiguration mode
2017-01-27 09:26:53 -05:00
be1328c55b
kcu105- added missing ethernet configurations
2017-01-23 10:14:09 -05:00
661413627f
daq3- round about way to avoid ip getting locked
2017-01-20 15:55:33 -05:00
62792ddaed
adrv9371x: Change the axi_adxcvr cores addresses
...
Because the S_AXI interface of the axi_adxcvr core was infered
using the process adi_ip_properties, the interface address range
has changed from 4k to 64k. As a result, all the addresses of
the axi_adxcvr cores were changed and realigned.
2017-01-19 15:23:03 +02:00
ecd152c90d
pzsdr1: ccbrk_cmos, fix clkdiv parameters
2017-01-18 12:04:04 +02:00
165ba76d9d
pzsdr1: Added FIFOs for DAC and ADC paths so that they work at l_clk or l_clk/2
2017-01-18 12:01:24 +02:00
319a883c00
pzsdr2: Added FIFOs for DAC and ADC paths so that they work at l_clk/2 or l_clk/4
2017-01-18 12:00:10 +02:00
9344dd34dc
zcu102: Update project to include clkdiv
2017-01-16 14:47:31 +02:00
4dcad7e116
fmcomms2: zcu102, update clkdiv device parameter
2017-01-16 14:38:37 +02:00
Lars-Peter Clausen
AndreiGrozav
Adrian Costina
Istvan Csomortani
Rejeesh Kutty