32d46389f2
adrv9371x: Move GTs AXI interface to HP3
...
If the VDMA and the GTs AXI are connected to the same HP port, the
HDMI won't work on full resolution (1080p). Care should be taken, this can
affect the receive and observation paths (both are connected to HP2).
2016-05-27 14:13:55 +03:00
b452a8e2d4
adrv9371x: Connect bypass and data underflow
2016-05-27 14:13:55 +03:00
3859cba186
adrv9371x/zc706: Add PL_DDR FIFO to the design
2016-05-27 14:13:55 +03:00
d0b40afb45
zc706/common: Fix PL_DDR3 fifo integration script
2016-05-27 14:13:55 +03:00
aca3038919
axi_dacfifo: No overflow for DAC
2016-05-27 14:13:55 +03:00
81ade7f26c
axi_dacfifo: Fix resets
...
DMA side: axi_resetn is used to reset the address counters
DAC side: GT tx_rst is used to reset the last_address register
2016-05-27 14:13:55 +03:00
578376c8fe
axi_dacfifo: Add bypass logic
2016-05-27 14:13:55 +03:00
9c6e80fca2
daq3/a10gx- qsys modifications
2016-05-24 03:15:45 -04:00
39d23032f1
daq2- qsys updates
2016-05-23 10:55:44 -04:00
0d1c4d232e
a10soc- updates-1
2016-05-20 16:14:57 -04:00
09520709b0
make updates
2016-05-20 12:35:45 -04:00
f92e8509bb
adrv9371x- added
2016-05-20 11:46:25 -04:00
50d018fc11
arradio- rfifo/wfifo added
2016-05-18 13:24:13 -04:00
e345953bdd
arradio- updates
2016-05-16 12:19:38 -04:00
72151bb1a6
a10gx: Updated base design to include MMU
2016-05-13 18:44:41 +03:00
f3f5353944
zcu102- updates
2016-05-10 15:40:41 -04:00
16e3a0e569
zcu102- updates
2016-05-10 15:40:41 -04:00
e1350018da
zcu102- updates
2016-05-10 15:40:41 -04:00
a6411dbd63
zcu102- added
2016-05-10 15:40:41 -04:00
e8fbdd0f5d
zcu102: zynq ultrascale
2016-05-10 15:40:41 -04:00
0041bf69be
c5soc- remove unused hps ports
2016-05-09 13:54:08 -04:00
89b20f2a35
c5soc- remove unused hps ports
2016-05-09 13:54:08 -04:00
8d72b645ae
fmcomms2/common: Remove ila_tdd block
2016-05-09 10:28:10 +03:00
b0538a03a2
Make: Update
2016-05-06 16:44:24 +03:00
4863a04132
axi_adc/dacfifo: Split the intergration script file
...
Split the integration script file into two separate script files. Rename the
integration processes names to be more meaningful.
2016-05-05 09:53:55 +03:00
ddfaff2cf5
fmcomms2/a10soc: compile version
2016-05-04 13:42:12 -04:00
f4e5965936
fmcomms2/a10soc: ip updates
2016-05-04 13:42:12 -04:00
92dcce1674
a10soc: default ports
2016-05-04 13:42:12 -04:00
be74db656c
ad6674evb, fmcadc2, fmcadc4, fmcadc5, fmcjesdadc1:
...
Update system_project.tcl scripts to correctly select the necessary
constraint files
2016-05-04 19:37:33 +03:00
3ca3414522
fmcadc2: Fixed bus data width
2016-05-04 19:20:01 +03:00
9104b2cc60
ad6676evb, fmcadc2, fmcadc4, fmcadc5,...
...
ad6676evb, fmcadc2, fmcadc4, fmcadc5, fmcjesdadc1: Remove unused
set_proprieties
2016-05-04 19:13:25 +03:00
385ed31a45
make files update
2016-04-29 10:17:35 -04:00
61b531b1c1
a10soc device update
2016-04-29 10:17:35 -04:00
160d54f311
ad7616_sdz: Some comment rephrase
2016-04-29 16:41:35 +03:00
664ea16a0f
ccpci- carrier changes
2016-04-27 16:26:11 -04:00
e790e4c3ae
a10soc- complete qsys
2016-04-25 12:56:19 -04:00
bfa6fe2a40
a10soc- updates
2016-04-25 11:23:16 -04:00
28159aeec9
a10soc- updates
2016-04-25 11:11:46 -04:00
0a3967b886
a10soc- updates
2016-04-25 10:53:26 -04:00
d36d1263c5
a10soc- updates
2016-04-25 10:50:09 -04:00
1fd5c0f28b
ad7616_sdz: Fix IO definitions for the parallel interface.
2016-04-25 10:56:45 +03:00
6de356e8fc
ad7616_sdz: Fix the data width at i_iobuf_adc_cntrl
2016-04-25 10:55:37 +03:00
2a5f31d26b
fmcomms2/a10soc- copy
2016-04-22 15:15:44 -04:00
82c4f75f13
a10soc- a10gx copy
2016-04-22 10:39:21 -04:00
7a4a7edfba
daq2/a10gx: 10AX115S3F45E2SGE3 version
2016-04-20 16:07:41 -04:00
e00236e5fd
daq2/a10gx: 10AX115S3F45E2SGE3 version
2016-04-20 16:04:46 -04:00
8b2542b181
daq2/a10gx: 10AX115S3F45E2SGE3 version
2016-04-20 16:01:12 -04:00
679d471d75
Merge branch 'hdl_2016_r1' into dev
...
hdl_2016_r1 contains IP core upgrades to Vivado 2015.4.2 and hdmi_tx improvements.
2016-04-19 18:05:50 +03:00
402253d308
usb_fx3: Updated design to include the GPIF II interface
2016-04-19 15:52:30 +03:00
8a574cd8ba
zc706_system_plddr3.tcl : Add integration process for the AXI_DAC_FIFO
2016-04-19 11:30:52 +03:00
c291f8f107
daq1: Updated design to 2015.4
2016-04-14 23:36:47 +03:00
469b4ea5e8
fmcadc5: Updated design to 2015.4
2016-04-14 23:18:23 +03:00
62bd057106
fmcadc5/common: Update common design to 2015.4
2016-04-14 23:01:38 +03:00
a88ced8136
pzsdr1: lvds/cmos updates
2016-04-11 16:18:29 -04:00
3006c5a223
make updates
2016-04-11 16:14:59 -04:00
736bbdd95a
pzsdr1- io updates
2016-04-11 16:12:21 -04:00
8a5a5082f3
pzsdr1- io updates
2016-04-11 16:12:09 -04:00
8e689f4594
pzsdr1- lvds/cmos constraints
2016-04-11 16:00:18 -04:00
7e807d83b1
pzsdr1- cmos mode
2016-04-11 15:58:29 -04:00
bf6ef4e5f3
board- add disconnect
2016-04-11 15:33:00 -04:00
68bc647472
pzsdr1- ddr board delays update
2016-04-06 15:30:27 -04:00
21208ca208
Makefiles: Update Makefiles
2016-03-31 12:37:47 +03:00
1fab6ce477
daq2/common: Add util_dacfifo/dac_xfer_out control
2016-03-29 16:55:33 +03:00
255b0ebd40
util_dacfifo: Add dac_xfer_out control
...
The dac_xfer_out control signal is asserted while the DAC reads back data. Should be connected to upack/dma_xfer_in.
2016-03-29 16:50:00 +03:00
657144d9a7
a10gx: Updated base design and DAQ2 to the new revision of the a10gx board
...
- tried using ATX PLL and fPLL for TX transceiver clocks, but could not get them to lock
- CMU PLL works correctly as temporary solution
2016-03-28 13:21:36 +03:00
7ce3f6e274
ad7616_sdz: Fix system top for parallel interface mode.
2016-03-24 13:49:30 +02:00
a1c2c61884
ad7616_sdz: Update the IOBUF instance names
2016-03-24 11:46:33 +02:00
7c2f34549b
motcon2_fmc: Update common design to 2015.4
2016-03-23 10:27:07 +02:00
373481360b
util_dacfifo: Add a bypass option to the FIFO
2016-03-21 14:14:43 +02:00
714caa964c
usdrx1: Update common design to 2015.4
2016-03-18 16:29:43 +02:00
05f4f3ac09
usb_fx3: Update common design to 2015.4
2016-03-18 16:16:38 +02:00
24fdd2b9b7
pzsdr/ccpci: Update common design to 2015.4
2016-03-18 15:30:10 +02:00
f8b155faab
pzsdr/ccfmc: Update common design to 2015.4
2016-03-18 15:28:56 +02:00
d567af54ef
imageon: Update common design to 2015.4
2016-03-18 15:27:31 +02:00
995debedce
fmcomms2: Update common design to 2015.4
2016-03-18 15:26:52 +02:00
b555be25d5
kcu105: Update common design to 2015.4
2016-03-18 15:22:42 +02:00
412013d939
adv7511: Update common design to 2015.4
2016-03-18 15:01:25 +02:00
d355aa0ea6
daq3/zc706: Updated design to 2015.4
2016-03-17 11:46:48 +02:00
012b095006
daq3: Updated common design to 2015.4
2016-03-17 11:44:27 +02:00
38c3f7474a
ad6676: Updated common design to 2015.4
2016-03-17 11:40:46 +02:00
abc03fff2c
fmcomms7: Updated design to 2015.4
2016-03-17 09:11:41 +02:00
59c726ecbe
fmcjesdadc1: Updated common design to 2015.4
2016-03-16 10:14:06 +02:00
1a3aab0c13
fmcomms1: Updated common design to 2015.4
2016-03-16 10:09:54 +02:00
b7be089b82
daq2: Updated common design to 2015.4
2016-03-16 10:02:42 +02:00
697469ee28
daq1- updates
2016-03-15 12:39:38 -04:00
334fce03a3
fmcadc4/zc706: Updated design to 2015.4
2016-03-15 15:28:11 +02:00
e8dd5f9788
fmcadc4: Updated common design to 2015.4
2016-03-15 15:27:25 +02:00
98cc7dad7d
fmcadc2: Updated common design to 2015.4
2016-03-15 15:26:05 +02:00
ceea7f25b2
fmcomms2: Updated common design to 2015.4
2016-03-15 15:23:20 +02:00
6f03998b95
zc702: Updated common design to 2015.4
2016-03-15 15:21:22 +02:00
a0c5f46940
zed: Updated common design to 2015.4
2016-03-15 15:20:46 +02:00
9a258d5e4c
vc707: Updated common design to 2015.4
2016-03-15 15:20:02 +02:00
bcf5bd8137
mitx045: Updated common design to 2015.4
2016-03-15 15:18:31 +02:00
27f5f1dcbe
kc705: Updated common design to 2015.4
2016-03-15 15:17:53 +02:00
eb743e0e03
ac701: Updated common design to 2015.4
2016-03-15 15:17:02 +02:00
d282064103
zc706: Updated common design to 2015.4
2016-03-15 15:16:36 +02:00
71be9519ec
adi_project.tcl: Updated to 2015.4
2016-03-15 15:03:50 +02:00
33b265a742
Makefile: Update Makefiles
2016-03-14 09:31:17 +02:00
561412e322
pzsdr-cmos swap
2016-03-11 11:25:58 -05:00
c7ee15d4f4
ccbrk_cmos: cmos mode
2016-03-11 11:25:58 -05:00
c566784ba9
ccbrk_cmos: ccbrk copy
2016-03-11 11:25:58 -05:00
573146aa96
axi_ad7616: Fix the data width of the AXI stream interface
2016-03-10 16:38:53 +02:00
b0f90bd0e8
daq1/cpld: Read interface fix
2016-03-04 20:28:24 +02:00
7e607957ee
daq1.cpld: Prevent the spi_counter to roll over.
2016-03-04 20:28:22 +02:00
262a42c676
daq1/cpld: Update CPLD_VERSION value
2016-03-04 20:28:20 +02:00
9439862301
daq1/cpld: Update CPLD
...
Change to control line fpga_to_cpld to cpld_to_fpga, this is not a functional change.
2016-03-04 20:28:18 +02:00
3466f21f8e
pzsdr add cmos/lvds support
2016-03-04 10:39:48 -05:00
18f30c8dc8
pzsdr- cmos/lvds split
2016-03-04 10:39:48 -05:00
a2374f64bf
pzsdr- cmos/lvds split
2016-03-04 10:39:48 -05:00
977d9d0624
Merge branch 'hdl_2015_r2' into dev
...
Conflicts:
projects/daq1/common/daq1_spi.v
2016-03-02 13:52:15 +02:00
40fb68dfd5
ad9265, ad9434, ad9467, daq1, daq2, daq3, fmcadc2, fmcadc4, fmcadc5, fmcjesdadc1, fmcomms6, fmcomms7, usdrx1: updated common spi module so that spi streaming is possible
2016-03-02 13:39:37 +02:00
becc23a69b
daq2: Modified common spi module so that spi streaming is possible
...
- stop incrementing spi_count after the instruction cycle
2016-03-01 17:25:58 +02:00
f7e490c2b3
hdlmake.pl updates
2016-02-26 13:46:11 -05:00
e012d0519b
Merge remote-tracking branch 'origin/hdl_2015_r2' into dev
2016-02-26 13:39:39 -05:00
f6e64e42b0
kcu105: add ethernet idelaycntrl
2016-02-26 13:19:49 -05:00
59313f3c90
daq1: ADC DMA must be in none-cyclic mode
2016-02-24 14:37:19 +02:00
c0a559a9b1
daq1: Fix some typos in the SPI wrapper
2016-02-24 14:31:56 +02:00
8ccd8d87bb
daq2: A10GX, increase analog/digital reset durations
...
- reset the xcvr_rst_cntrl only from the axi_jesd_xcvr
- checked separate RX/TX reset per channel
2016-02-23 11:41:38 +02:00
89f7aadfb1
fmcjesdadc1: A5GT, connected xcvr_rxt_cntrl reset input to the axi_jesd_xcvr reset output
...
This will allow for the transceivers to be reset by the axi_jesd_xcvr core
2016-02-23 11:31:07 +02:00
4fb6589b2d
pzsdr/ccfmc: add fan controls
2016-02-19 16:40:54 -05:00
377461e0d4
Merge branch 'hdl_2015_r2' into dev
2016-02-19 14:15:27 +02:00
0f37dd6424
fmcjesdadc1: Fixed project
...
- changed system_project.tcl so that all base designs to be included
- changed DMA properties to take into consideration the new parameter names
- changed reset bridges to asynchronous
- increased maximum burst size of the DMA bridge
- changed the data_width of the memory bus to 256, as with 512 timing violations may occur
- changed base addresses for the base system to be the same as in the previous release
2016-02-19 14:09:57 +02:00
ce760eb691
fmcadc2- add adf4355 access
2016-02-18 16:17:33 -05:00
d94f157454
arradio: Changed ADC/DAC DMA address length to 24 bit
2016-02-16 15:27:51 +02:00
43e03ca6f7
arradio: Updated project
...
- made the reset bridges asynchronous
- connected the arradio gpio to the CPU interconnect
2016-02-16 14:50:23 +02:00
5518c47ca4
daq1_cpld: Set Input and tristate I/O termination mode to FLOAT
2016-02-15 19:27:59 +02:00
051ac307e6
daq1_cpld: Do not forward the first eight clock cycles of fmc_spi_sclk to sclk
2016-02-15 19:26:58 +02:00
9370246cfa
daq1: Fix bugs on CPLD design
...
Fix the CSN forwarding.
2016-02-12 16:59:09 +02:00
5ed2c0b599
daq1: Update CPLD constraints file
2016-02-12 16:54:36 +02:00
aa2ff0223a
daq1: Update CPLD design
...
+ SPI counter counts on negative edge of the SPI_CLK
+ Shift register for read, shifting MSB first
+ Fix write access logic
+ Update the internal register addresses
2016-02-12 14:45:18 +02:00
c32d7147d5
daq1 : There is a single CSN from master
2016-02-12 14:38:32 +02:00
9675df15c6
daq1_zc706: Update constraints file
2016-02-12 14:37:02 +02:00
e381d5170c
util_tdd_sync: Update the synchronization interface
...
Simplify the synchronization interface, there is one signal line between the synchronization module and transceiver core.
2016-02-12 14:27:37 +02:00
61f9f72a75
fmcjesdadc1: Updated VC707 project for maximum throughput from DMA to DDR
...
- Increased the DMAs internal FIFO
2016-02-09 12:30:56 +02:00
c431adb793
fmcjesdadc1: Updated KC705 project for maximum throughput from DMA to DDR
...
- Increased the DMA internal FIFO
2016-02-09 12:00:27 +02:00
ad9ecbbbb6
daq2: Updated a10gx project to quartus 15.1.1
2016-02-05 17:43:05 +02:00
a74e2061e9
ad7616_sdz: BUSY is input for the FPGA
2016-02-03 14:12:00 +02:00
bb62f6d225
pzsdr1- updates
2016-02-02 12:34:09 -05:00
41b6ebeeaf
pzsdr1- updates
2016-02-02 12:33:55 -05:00
b147e9c94a
pzsdr1- updates
2016-02-02 12:33:01 -05:00
59783f6cff
ad7616_sdz: Add support for Zedboard
2016-01-29 15:28:06 +02:00
122667259f
ad7616_sdz: Update Make file
2016-01-28 14:48:44 +02:00
118577f64f
ad7616_sdz: Add support for parallel interface
2016-01-28 12:38:22 +02:00
170295161f
pzsdr1- xdc
2016-01-26 11:19:00 -05:00
cd43ebd8bc
axi_ad7616: The OP_MODE parameter is no longer required
2016-01-26 11:05:33 +02:00
bcac3eef4d
pzsdr1- initial commit
2016-01-25 16:07:33 -05:00
44a382fc69
pzsdr1-added
2016-01-25 15:33:34 -05:00
2a17ce275c
axi_ad7616: Control inputs are controlled through GPIO
...
The following control inputs are controlled through GPIO: reset_n, seq_en, hw_rngsel, chsel, crcen, burst and os.
2016-01-25 17:50:50 +02:00
e22d5d5c18
daq2: Fix clock constraints for KC705 and VC707
2016-01-22 19:09:57 +02:00
59fbd99fdb
fmcjesdadc1: Added clock constraint for the ADC path
2016-01-22 15:46:20 +02:00
dca39c26f9
ad6676evb: Added clock constraint for the ADC path
2016-01-22 15:45:16 +02:00
9cd0378003
fmcadc2: Added clock constraint for the ADC path
2016-01-22 15:44:04 +02:00
aa77af6bdf
daq1_cpld: Add ISE project file
...
This file, along with the project source files, is sufficient to open and implement in ISE Project Navigator.
2016-01-21 18:05:59 +02:00
14f7027793
ad7616_sdz: Move the context switching to system_project.tcl
2016-01-19 11:34:28 +02:00
8c69c9d2ce
daq1_zc706 : Update the project
...
+ Add AD9684 to the block design
+ Update the IO definitions
+ Update the CPLD design
+ Add 3wire SPI logic
2016-01-19 11:20:35 +02:00
ab99c4456a
ad9434_fmc: Delete unnecessary set_property call
...
HPx interface is activated by the ad_mem_hpx_interconnect process
2016-01-14 15:41:23 +02:00
c094ab8b52
cn0363: Add support for the MicroZed
...
Add support for connecting the CN0363 to the MicroZed. This works in
combination with the MicroZed Arduino carrier board. The CN0363 needs to be
connected to the PLPMOD header.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-01-13 20:32:26 +01:00
514eb68876
cn0363: Factor out common parts
...
Factor out the common parts of the cn0363 design so we can use it to add
support for other carriers.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-01-13 20:32:26 +01:00
d2b26720e6
common: microzed: Add clock, reset and interrupt support
...
In order for the base project to be usable by other projects it needs to
create the clock, reset and interrupt signals that are expected to exist.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-01-13 20:32:26 +01:00
51d20b1a61
adi_project.tcl: Add MicroZed support
...
Handle the projects for the MicroZed and set up the FPGA part accordingly.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-01-13 20:32:26 +01:00
426490c394
common: Rename uzed to microzed
...
Everybody calls the MicroZed microzed in their projects. Don't deviate from
that to avoid potential confusion.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-01-13 20:18:57 +01:00
c397787001
uzed: updates
2016-01-11 15:36:01 -05:00
a610ebb413
uzed: zed-copy
2016-01-11 13:53:22 -05:00
02cc926275
daq1: Add CPLD logic and IO constraints
2016-01-04 18:10:46 +02:00
7013b319b0
motcon2_fmc: Fixed reset connection for cpack cores
2015-12-22 12:03:34 +02:00
17e7d1b86f
ad7616: Add Makefiles
2015-12-21 17:09:42 +02:00
2bb19be3d3
pzsdr/ccfmc: sfp io control
2015-12-17 16:18:06 -05:00
f3fe16a102
pzsdr/ccfmc: camera/sfp pin changes
2015-12-17 16:17:24 -05:00
ea045a3f9a
fmcadc4: change qpll to receive
2015-12-17 12:34:47 -05:00
40ab2f5e6a
ccfmc: tdd/gpio bit moved to the top
2015-12-17 11:37:57 -05:00
34b832e22a
fmcomms6: Fixed reset connection for cpack core
2015-12-16 10:36:33 +02:00
35f6bd16e9
fmcomms5: Fixed reset connection for cpack core
2015-12-16 10:34:36 +02:00
83fd4a53a7
daq3/kcu105: updates
2015-12-14 09:29:48 -05:00
07316a905e
daq3/a10gx: sysref is lvds
2015-12-14 09:29:10 -05:00
ee4d5af12e
ad7616_sdz: Update the project
...
+ Fix system_top.v
+ Finish up the common block design
+ Fix system_project.tcl
2015-12-14 16:02:38 +02:00
f4e3523390
ad7616_sdz: Update IO constraints
2015-12-14 15:34:56 +02:00
6a9d1c431a
daq3/a10gx: updated to a10gx/quartus
2015-12-11 12:49:25 -05:00
da2e1bdc9a
daq2/a10gx: 32bits generic gpio
2015-12-11 11:50:26 -05:00
650d426301
a10gx/base: set gpio to 32
2015-12-11 10:14:37 -05:00
dc84a9ad82
daq3/a10gx: updates
2015-12-10 16:06:14 -05:00
f1b6577447
a10gx/base: separate gpio in/out
2015-12-10 16:04:54 -05:00
d944198212
daq3/a10gx: board updates
2015-12-10 09:45:20 -05:00
1a38ea205d
daq3/a10gx: copy
2015-12-10 09:42:56 -05:00
614babc18e
daq3/kcu105: copy
2015-12-10 09:41:47 -05:00
b0fef1122e
daq3/a10gx: copy
2015-12-10 09:41:37 -05:00
be075379df
hdlmake: updates
2015-12-07 13:11:24 -05:00
0938041d97
ad7768evb: added
2015-12-07 13:07:03 -05:00
6e549171f0
fmcomms5: Connected the clk input of the ad9361 to l_clk
2015-12-02 14:43:44 +02:00
2309c4d83c
Makefiles: Removed " from path
2015-11-27 14:02:46 +02:00
159f6c1216
Makefiles: Updated Makefiles
...
- for altera projects, taken into consideration of the new location for common qsys files
- for fmcomms5, added wfifo dependency
- for daq3, added mfifo dependency
2015-11-27 12:39:42 +02:00
36febf8591
Merge branch 'master' into dev
...
Conflicts:
library/axi_ad9361/axi_ad9361_ip.tcl
library/axi_dmac/Makefile
library/axi_dmac/axi_dmac_constr.ttcl
library/axi_dmac/axi_dmac_ip.tcl
library/common/ad_tdd_control.v
projects/daq2/common/daq2_bd.tcl
projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl
projects/fmcomms2/zc706pr/system_project.tcl
projects/fmcomms2/zc706pr/system_top.v
projects/usdrx1/common/usdrx1_bd.tcl
This merge was made, to recover any forgotten fixes from master,
before creating the new release branch. All conflicts were reviewed
and resolved.
2015-11-26 13:38:11 +02:00
ea57b3c03c
daq2: A10GX, add project specific IP search paths
2015-11-25 10:58:36 +02:00
e8a595b81e
fmcjesdadc1: Updated a5soc design
2015-11-24 15:39:52 +02:00
fd3910a915
fmcjesdadc1: Updated a5gt design
2015-11-24 15:39:21 +02:00
9281eb2c33
fmcjesdadc1: Updated common altera design
2015-11-24 15:38:58 +02:00
a81625e1fa
daq2: Updated a10gx project
2015-11-24 13:28:53 +02:00
605a0768e0
arradio: Updated c5soc project
2015-11-24 13:27:44 +02:00
a0e67aad56
c5soc: Updated common design
2015-11-24 13:22:01 +02:00
c051a578e5
fmcomms2: Delete unnecessary clock definition
...
The two clocks, rx_clk and ad9361_clk, are the same.
2015-11-20 19:35:37 +02:00
c15c82d9d1
ccpci- remove ps7 ddr hp0 access
2015-11-19 16:42:02 -05:00
Istvan Csomortani
Rejeesh Kutty
Adrian Costina
AndreiGrozav
István Csomortáni
Lars-Peter Clausen