7 Commits (e4832cd027e0a27d6fdd31a2aab9780827b9b720)

Author	SHA1	Message	Date
Istvan Csomortani	20b0c92a1f	iodelay: Expose the REFCLK_FREQUENCY parameter	2019-06-11 18:13:06 +03:00
Istvan Csomortani	70b7d69ff8	whitespace: Delete all trailing white spaces	2019-06-07 10:20:15 +03:00
AndreiGrozav	66823682b6	Add FPGA info parameters flow ... Common basic steps: - Include/create infrastructure: * Intel: - require quartus::device package - set_module_property VALIDATION_CALLBACK info_param_validate * Xilinx - add bd.tcl, containing init{} procedure. The init procedure will be called when the IP will be instantiated into the block design. - add to the xilinx_blockdiagram file group the bd.tcl and common_bd.tcl - create GUI files - add parameters in *_ip.tcl and *_hw.tcl (adi_add_auto_fpga_spec_params) - add/propagate the info parameters through the IP verilog files axi_clkgen util_adxcvr ad_ip_jesd204_tpl_adc ad_ip_jesd204_tpl_dac axi_ad5766 axi_ad6676 axi_ad9122 axi_ad9144 axi_ad9152 axi_ad9162 axi_ad9250 axi_ad9265 axi_ad9680 axi_ad9361 axi_ad9371 axi_adrv9009 axi_ad9739a axi_ad9434 axi_ad9467 axi_ad9684 axi_ad9963 axi_ad9625 axi_ad9671 axi_hdmi_tx axi_fmcadc5_sync	2019-03-30 11:26:11 +02:00
AndreiGrozav	251ea9471c	Remove Xilinx 6 series support ... The primitives are not used or supported by the newer versions of Vivado.	2018-10-17 10:06:40 +03:00
Istvan Csomortani	425e803364	license: Fix a spelling mistake	2018-04-11 15:09:54 +03:00
Rejeesh Kutty	704512f0d4	library/xilinx/common- add iodelay group	2017-07-25 10:22:52 -04:00
Rejeesh Kutty	b65802ee1e	library/xilinx- lvds/cmos integration	2017-07-24 16:28:50 -04:00