Rejeesh Kutty
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39fdf11ef3
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util_adxcvr- rx/tx clocks
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2016-10-05 13:53:02 -04:00 |
Istvan Csomortani
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7ec93ce8e0
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util_adxcvr: Fix some typo
GTHE4_CHANNEL is instantiated in case of XCVR_TYPE == 2
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2016-10-05 17:42:12 +03:00 |
|
Istvan Csomortani
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4f587d2e48
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util_adxcvr: Delete trailing whitespaces
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2016-10-05 17:41:40 +03:00 |
|
Rejeesh Kutty
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48dd4880a3
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util_adxcvr- ultrascale+ initial commit
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2016-10-03 16:11:45 -04:00 |
|
Rejeesh Kutty
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0e8551545c
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util_adxcvr- ultrascale+ initial commit
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2016-10-03 16:11:45 -04:00 |
|
Rejeesh Kutty
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b4652650e4
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util_adxcvr- xcvr_type parameter
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2016-10-03 16:11:45 -04:00 |
|
Rejeesh Kutty
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63ddcf1e26
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util_adxcvr- synthesis warnings fix
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2016-10-03 16:11:45 -04:00 |
|
Rejeesh Kutty
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6b956066ef
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xilinx/ad_lvds*- ultrascale+
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2016-09-30 11:55:10 -04:00 |
|
Rejeesh Kutty
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9defccef70
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dacfifo- axi address map fixes
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2016-09-27 14:48:23 -04:00 |
|
Rejeesh Kutty
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21b5e9c634
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hdlmake- updates
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2016-09-21 11:56:03 -04:00 |
|
Rejeesh Kutty
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0def596b43
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axi_xcvrlb- updates
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2016-09-21 11:04:22 -04:00 |
|
Rejeesh Kutty
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d497a7b0ae
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axi_xcvrlb- constraints
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2016-09-21 11:04:22 -04:00 |
|
Rejeesh Kutty
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1860d72df6
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axi_xcvrlb- updates
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2016-09-19 12:39:59 -04:00 |
|
Rejeesh Kutty
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5592c2780e
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axi_xcvrlb- loopback version
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2016-09-19 12:39:59 -04:00 |
|
Istvan Csomortani
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38f1521861
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xilinx/ad_serdes_in : Fix some typos
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2016-09-19 16:02:52 +03:00 |
|
Istvan Csomortani
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ff0f659a33
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xilinx/ad_serdes_clk : Rename parameter MMCM_DEVICE_TYPE to DEVICE_TYPE
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2016-09-19 16:02:06 +03:00 |
|
Istvan Csomortani
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6510f92c12
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ad_serdes : Cosmetic changes
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2016-09-16 14:45:39 +03:00 |
|
Rejeesh Kutty
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a2d15acb89
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ad_serdes- altera/xilinx sync
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2016-09-15 13:33:55 -04:00 |
|
Istvan Csomortani
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3b0c1e02fc
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axi_dacfifo: Move IP to library/xilinx
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2016-09-15 11:38:16 +03:00 |
|
Istvan Csomortani
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3cbbc771a8
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axi_adcfifo: Move IP to library/xilinx
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2016-09-15 11:36:47 +03:00 |
Shrutika Redkar
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10b9a0e52f
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upadated xcvr ips
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2016-08-17 15:51:55 -04:00 |
|
Rejeesh Kutty
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3427965cd2
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adxcvr- add u-gth bufg
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2016-08-11 10:00:41 -04:00 |
|
Shrutika Redkar
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829e4155ca
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modified transceiver configuration files
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2016-08-10 14:59:38 -04:00 |
|
Istvan Csomortani
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1d33d7d7ee
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lib_refactoring: Move the CMOS interface modules to ~/library/xilinx/common
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2016-08-08 15:07:42 +03:00 |
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Istvan Csomortani
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b806fa3b42
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lib_refactoring: Move all the Xilinx common modules to library/xilinx/common
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2016-08-08 15:06:10 +03:00 |
Adrian Costina
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5faf4c4976
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cleanup: Don't need Makefiles specific to xilinx/altera libraries. Top Makefile covers them
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2016-08-05 16:27:52 +03:00 |
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Adrian Costina
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d60bce654c
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Makefiles: Updated Makefiles so they run correctly with gnuwin32 tools
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2016-08-05 15:16:04 +03:00 |
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Rejeesh Kutty
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cb23ba8bb7
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make- script needs update
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2016-08-04 14:17:04 -04:00 |
|
Rejeesh Kutty
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e42b4ea378
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hdlmake- updates
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2016-08-04 13:28:25 -04:00 |
|
Rejeesh Kutty
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2b7c976be5
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xcvr- altera/xilinx split
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2016-08-04 13:26:10 -04:00 |