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5377 Commits (e51d9372cd03aed9871747cf2ec55a8210981226)

Author SHA1 Message Date
Adrian Costina e51d9372cd fmcomms8: ZCU102: Added DAC FIFO 2020-02-10 11:23:52 +02:00
Adrian Costina 016a1d540d fmcomms8: ZCU102: Initial commit 2020-02-10 11:23:52 +02:00
Laszlo Nagy ea06fcd7b6 util_adxcvr: add GTY4 parameters for 15.5Gbps lanerate 2020-02-10 09:48:17 +02:00
Laszlo Nagy 10a808b504 ad9208_dual_ebz/vcu118: remove GTY prefix from parameters 2020-02-10 09:48:17 +02:00
Laszlo Nagy 253b1149ad library/xilinx/util_adxcvr: merge GTY and GTH prefixed parameter 
parameters with same names were duplicated with transceiver specific
names due different default values.
This does not scales very well.

Use same name for the parameters as for other parameters and do the
default value handling in the IP configuration layer.
 2020-02-10 09:48:17 +02:00
Laszlo Nagy 9cce513645 jesd204/axi_jesd204_tx: Update version 2020-02-10 09:47:07 +02:00
Laszlo Nagy b8e1daa22b jesd204/axi_jesd204_rx: Update version 2020-02-10 09:47:07 +02:00
Laszlo Nagy 587a3c1a8d scripts/jesd204.tcl: Added 64b mode to Rx scripting 2020-02-10 09:47:07 +02:00
Laszlo Nagy 72186324f3 tb/loopback_64b_tb: Testbench for 64b mode 
Data integrity check over a loopbacked link.
 2020-02-10 09:47:07 +02:00
Laszlo Nagy bd9836886f jesd204_rx_static_config: Added 64b mode to Rx static config 2020-02-10 09:47:07 +02:00
Laszlo Nagy c3afbbc8a8 jesd204/interfaces: Added 64b mode Rx signals 2020-02-10 09:47:07 +02:00
Laszlo Nagy 7cad1f81d9 axi_jesd204_rx: Added 64b mode 2020-02-10 09:47:07 +02:00
Laszlo Nagy d1072847df jesd204_rx: 64b mode support for receive peripheral 
Instantiate 64B/66B decoder based on synthesis parameter.
 2020-02-10 09:47:07 +02:00
Laszlo Nagy 075f703443 jesd204_tx_static_config: Added 64b mode Tx static config 2020-02-10 09:47:07 +02:00
Laszlo Nagy e2d12a5b53 jesd204/scripts: Add 64b mode to Tx scripting 2020-02-10 09:47:07 +02:00
Laszlo Nagy c574861bf4 axi_jesd204_tx: Add 64b mode for control interface 2020-02-10 09:47:07 +02:00
Laszlo Nagy d9a31e8d83 jesd204_tx: Support for 64b mode in transmit peripheral 
Instantiate 64B/66B mode encoder based on synthesis parameter.
 2020-02-10 09:47:07 +02:00
Laszlo Nagy b40e055ebe jesd204/jesd204_common/jesd204_lmfc: Add multiblock clock edge, EoEMB 2020-02-10 09:47:07 +02:00
Laszlo Nagy 72e9a563da jesd204_common: Added JESD204C components 2020-02-10 09:47:07 +02:00
Laszlo Nagy 20ae7a8f7d jesd204: CRC12 component 
The component can be used in Tx to compute CRC on the data to be send as
in the Rx side to compute CRC on the received data.
 2020-02-10 09:47:07 +02:00
Laszlo Nagy a5346412d1 jesd204: Scrambler for 64b mode 
The component can be used for scrambling in Tx and descrambling on the
Rx side of the JESD link.
 2020-02-10 09:47:07 +02:00
Laszlo Nagy 474e07e579 jesd204: Add parameter for TPL data width 2020-02-10 09:47:07 +02:00
Laszlo Nagy f2060e27be jesd204_tx: add output pipeline stage 
In order to help timing closure on multi SLR FPGAs add a pipeline stage
between the link layer and physical layer. This will add a fixed amount
of delay to the overall latency.
 2020-02-07 09:02:46 +02:00
StancaPop 05c20af988
Merge pull request #430 from analogdevicesinc/update_tcl 
Rename projects for consistency
 2020-02-06 16:32:40 +02:00
AndreiGrozav e00ee136f6 cn0506_mii Updates for Rev B board 
Because of the rmii mode requirements(external 50MHz clock) the
board will have the rx_err signal replaced on the FMC connector with the
50MHz external clock (D08/D20).
The rx_er will be shifted to the D9/D21 pins.
 2020-02-03 11:20:18 +02:00
Istvan Csomortani b3e475cb8b ad_fmclidar1_ebz: Update the IO constraints to revB 
The IO location of the laser_driver_otw_n was moved from FMC_HPC_LA27_N
to FMC_HPC_LA31 (laser_gpio[12]).
laser_gpio[11:0] assignments were shifted with one bit to MSB, and laser_gpio[0]
got the old location of the laser_driver_otw_n.
 2020-01-31 18:47:37 +02:00
Arpadi 80a77b1e1b ad_rst_constr: Added the quiet option 
critical warnings were caused by this file when the ad_rst.v instantiation
was done using generate depending on a parameter (i.e. axi_spi_engine)
 2020-01-20 15:26:48 +02:00
Sergiu Arpadi 18a8ef8ad5 axi_generic_adc: Added constraints to ip 
ad_rst.v module was missing the xdc
 2020-01-17 16:46:31 +02:00
Sergiu Arpadi 135538b521 adi_project: Fixed kcu105 board file selection 2020-01-16 17:16:58 +02:00
AndreiGrozav db5e21cfb9 pluto revC: Add second RF channel 
-add second RF channel (without fir filters)
-use a more generic instantiation of the fir filters
-add util_cpack2 and util_upack2
 2020-01-16 11:40:28 +02:00
AndreiGrozav f9c8ff26cf pluto rev C hardware updates 
-connect axi_spi to board GPIOs
-connect axi IIC to board GPIOs

MIO49 SPI_CS   (PS MIO49)
L10P  SPI_MOSI (AXI_SPI)
L12N  SPI_MISO (AXI_SPI)
L24N  SPI_CLK  (AXI_SPI)
L7N   iic_sda  (AXI_IIC)
L9N   iic_scl  (AXI_IIC)
 2020-01-16 11:40:28 +02:00
Sergiu Arpadi e773b22087 adi_project: Updated board files version selection 
vivado will automatically select the latest version for a given board
 2020-01-14 17:16:01 +02:00
Stanca Pop fcf7bb035a ad40xx: Fix data_width definition 2020-01-14 15:24:43 +02:00
Arpadi ca623e4845 axi_laser_driver: Fixed reorder issue in ip tcl 2020-01-13 12:25:23 +02:00
Arpadi e6aa3a3b38 axi_ad9361: Fixed reorder issue in ip tcl 2020-01-13 12:25:23 +02:00
sarpadi afb28280c2 axi_gpreg: added constraints for clock_mon module 2020-01-13 12:25:23 +02:00
Istvan Csomortani 9caaba54d3 ad_mem_asym: Force the Xilinx synthesizer to infer Block RAMs 2020-01-13 12:25:23 +02:00
Arpadi d86fbb2a08 adi_board: fixed ddr memory mapping for microblaze projects 2020-01-13 12:25:23 +02:00
Arpadi 53cb087b9c ad_rst_constr: changed hier to hierarchical 2020-01-13 12:25:23 +02:00
Istvan Csomortani f07652ab5a axi_spi_engine: Add constraint for reset synchronizer 2020-01-13 12:25:23 +02:00
Istvan Csomortani 34ea5efdff adi_project_xilinx: Use the latest board files 2020-01-13 12:25:23 +02:00
Istvan Csomortani d2d7f2a3f9 up_clk_mon_constr: -heir is deprecated, use hierarchical instead 2020-01-13 12:25:23 +02:00
Istvan Csomortani 4511f731af axi_laser_driver: Fix ip.tcl file 
- Add a missing contraint file
  - Fix the path of the ttclk file
 2020-01-13 12:25:23 +02:00
Istvan Csomortani 87a752e242 ad_rst_constr: Search pin in all hierarchy 2020-01-13 12:25:23 +02:00
Istvan Csomortani adfeb435a4 scripts: Update Vivado version to 2019.1 2020-01-13 12:25:23 +02:00
Arpadi 25816ac1b3 adi_project_xilinx: removed set_property SCOPED_TO_REF 2020-01-13 12:25:23 +02:00
Laszlo Nagy c684c2cbd6 scripts/adi_ip_xilinx.tcl: add variable width for multi bus interfaces 
Bus sizes often depend on parameters. In such cases the physical indexes
of the interfaces from the multi bus must be calculated based on parameters.
For each interface expose the formula that calculates the indexes to the
block design.
 2020-01-13 09:55:25 +02:00
Stanca Pop fa259c7975 ad40xx: Fix a typo 2020-01-10 10:20:06 +02:00
cycollineau b93c1e6e90 intel/adi_jesd204: add bonded clock network support (#408) 
* jesd204b: add bonding clocks feature (fix for some routing issues)

* intel/adi_jesd204: bonding clock feature invisible in QSYS GUI if number of lanes is less than 6

* intel/adi_jesd204: clock network option renamed according to intel documentation

* intel/adi_jesd204: Hide BONDING_CLOCKS_EN parameter in RX mode

Co-authored-by: István Csomortáni <Csomi@users.noreply.github.com>
 2020-01-09 17:45:32 +02:00
Stanca Pop 9497b1cace ad40xx: Remove redundant upscaler IP, Add timing constraints 2020-01-09 11:32:31 +02:00