Istvan Csomortani
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fa32ea8f1f
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util_dacfifo: Fix the reset logic of the module
Both the DMA and DAC side should be in reset at the positive edge of the
dma_xfer_req, so we can re-initialize the buffer.
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2018-10-11 16:57:30 +03:00 |
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Istvan Csomortani
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6044aa3956
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util_dacfifo: Update the bypass logic
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2018-10-11 16:57:30 +03:00 |
Rejeesh Kutty
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7559d23873
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util_dacfifo/constraints- false paths for bypass
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2017-03-06 10:33:07 -05:00 |
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Istvan Csomortani
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760228d676
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util_dacfifo: Update the util_dacfifo
Fix bypass and undate the general functionality. If bypass enabled
the FIFO will function as a normal CDC FIFO.
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2017-03-03 18:43:36 +02:00 |
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Rejeesh Kutty
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104e9dfcdc
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adc/dac-fifo altera cores
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2017-02-28 13:30:50 -05:00 |