c2726ceac9
common:vcu118: move system memory to DDR C2
...
The DDR controller for C2 for is much closer to the transceivers which
connect to the FMCp connector so designs does not have to span over all
three SLRs just over two reducing implementation and timing closure effort.
2019-11-28 16:17:44 +02:00
0cb5c0bdaf
adv9009zu11eg: Update FPGA to -2. Update DDR4 clock frequency
2019-11-27 16:27:44 +02:00
c44b4957b5
ad7134_fmc/zed: Fix IO definitions for SDI lines
2019-11-27 10:04:37 +02:00
88e80f604e
daq3:zcu102: fix GPIO double drive
2019-11-26 14:41:19 +02:00
8c39cf8560
scripts: adi_board.tcl: Update the axi_adxcvr to util_adxcvr connections
2019-11-26 12:57:53 +02:00
8131c86f75
m2k: Connect the adc_trigger reset
2019-11-25 13:14:18 +00:00
a06c74edc7
fmcjesdadc1: Change rx_div_clk to 125MHz
2019-11-20 10:50:18 +02:00
9260979b15
adrv9364: Added sysid to all projects
2019-11-20 10:43:54 +02:00
570dae7df6
adrv9361: Added sysid to all projects
2019-11-20 10:43:54 +02:00
dfe3258a4f
adrv9009zu11eg: Add axi_sysid
2019-11-19 10:29:57 +02:00
81d3a9eb66
adrv9009zu11eg: Reduce SPI Clock speed to meet timing
2019-11-19 10:29:57 +02:00
4b380fe640
ad7768-1evb: Add coraz7s support
2019-11-15 14:35:00 +02:00
40d839df5f
coraz7s: Initial commit
2019-11-15 14:35:00 +02:00
514aadb54e
m2k: Use dac trigger
2019-11-15 12:23:01 +00:00
a589a2c7eb
adrv9009_zu11eg_som: Change design partitioning
...
Create a structure similar with ADRV936x projects
2019-11-14 15:25:23 +02:00
eab1e86544
adrv9364z7020: Rename *box project to *packrf
2019-10-29 16:07:08 +02:00
de324526e3
adrv9361z7035: Rename *box project to *packrf
2019-10-29 16:07:08 +02:00
fba7cac0c6
ad7768-1evb: Remove ADC2, update spi engine framework
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The second ADC was removed from the project, as the EV-AD7768-1FMCZ evaluation
board contains only one ADC. Therefore, all the IPs related to the
second ADC have been removed, too.
The data width supported by the spi IPs has been changed from 8 bits to
32 bits, therefore the axis_upscaler(util_axis_upscale_v1_0) and the
m_axis_samples_24(AXI4-Stream Data Width Converter) are no more necessary,
so they have been removed from the design.
The 24 bits width data transfer between the s_axis of axi_ad77681_dma
(AXI DMA Controller) and the offload_sdi of the spi_engine_offload is now made
directly.
2019-10-28 12:00:23 +02:00
4941d89fff
cn0506_mii: Add support on a10soc
2019-10-18 19:09:04 +03:00
fbb3a154ff
cn0506_mii: Add support on zcu102
2019-10-18 19:09:04 +03:00
3cb2392711
cn0506_mii: Add support on zc706
2019-10-18 19:09:04 +03:00
e98951d282
cn0506_mii: Add support on zed
2019-10-18 19:09:04 +03:00
8202c0025c
cn0506_mii: Common design initial commit
2019-10-18 19:09:04 +03:00
9323f4193c
m2k: Clean old interrupt connection style
2019-10-18 18:28:01 +03:00
a4547a32b6
pluto: Clean old interrupt connections style
2019-10-18 18:28:01 +03:00
fd4d32c408
projects/scripts/*xilinx*: Generate report utilization extra files
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Add commands to generate one extra file with resource utilization, in CSV format.
New commands executes only if ADI_GENERATE_UTILIZATION env variable is set.
2019-10-18 13:42:34 +03:00
5a4726b356
adrv9364z7020: Fix interrupt concatenation
2019-10-17 15:09:48 +03:00
f0f314f24b
adrv9361z7035: Fix interrupt concatenation
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None functional change, main goal is to increase consistancy in our
code base.
2019-10-17 15:09:48 +03:00
80333573c7
ad_fmclidar1_ebz/zcu102: Fix SYSREF input delay constraint
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Add one clock cycle input delay for the SYSREF input,
to compensate the high propegation delay of device_clk_BUFG.
2019-10-17 09:59:23 +03:00
03bec4b49c
ad_fmclidar1_ebz: Interchange SYSREF and DEV_CLK ports location
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In ZCU102 LA01_CC_P|N are connected to regional clock, but in order to
receive a device clock properly we have to use pin which is connected
to a global clock buffer. Luckily SYSREF is connected to global clock
pin; swap to port to receive the device clock correctly.
Also, swap the ports in both ZC706 and A10SOC carriers.
2019-10-17 09:59:23 +03:00
2cabf8d224
ad_fmclidar1_ebz: Move afe_iic definition to system_bd.tcl
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In order to prevent platform specific variable usage in the common tcl
script, move the AFE I2C interface definition to system_bd.tcl
2019-10-17 09:59:23 +03:00
b3e1cd2a15
ad_fmclidar1_ebz: Add support for ZCU102
2019-10-17 09:59:23 +03:00
3084a5d9aa
ad_fmclidar1_ebz/a10soc: Fix the comment about the carrier re-work
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The project is using the FMCA connector of the board. Make sure that all
the carrier re-work is related to the FMCA connector.
2019-10-17 09:58:52 +03:00
12c474ba13
ad7134: Change maximum data width from 24b to 32b
2019-10-16 17:35:24 +03:00
3c46cc9347
dac_fmc_ebz: Add project info to sys_id
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Add project device and mode info to sys_id custom string
2019-10-15 17:08:53 +03:00
58b846faae
dac_fmc_ebz: Add build time config option
2019-10-15 17:08:53 +03:00
e22016de4c
adrv9371/daq2/daq3:kcu105: patch GTH3 CPLL parameters
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Update GTH3 parameters according to a 10Gbps link from the Transceiver
Wizard.
2019-10-08 10:38:46 +03:00
8895b08eb1
adrv9009_zu11eg_som: i2s mclk fix
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mclk now generated by ps not axi clkgen ip. ADAU1761 expects a free
running clock and the i2s driver was switching the axi clkgen ip off
which was causing issues.
2019-10-03 17:30:57 +03:00
2344778dd8
ad_fmclidar1_ebz/a10soc: Initial commit
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Add initial support for Arria 10 SOC carrier.
2019-10-02 15:32:17 +03:00
23d29e7a15
a10soc_system_qsys: sys_dma_clk clock_source inherit its clock frequency from its source
2019-10-02 15:32:17 +03:00
af94487f57
adi_project_intel: Enable HPS internal timing
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It's recommended to use this global assignment so the tool can make a
more in-depth timing analysis.
2019-10-02 15:32:17 +03:00
bc2f916dfc
a10soc: Synchronize resets to the reset source
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Resets de-assertion should be synchronized to its associated clock.
2019-10-02 15:32:17 +03:00
9c9ce928d8
Merge pull request #346 from analogdevicesinc/spi_engine_trigger_update
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spi_engine: Update pulse generation
2019-10-02 14:42:41 +03:00
75d263afc5
adi_project_xilinx: Add constraint files to constr_1 file set
2019-09-27 18:21:25 +03:00
64e54fda8d
fmcomms5: remove clock skew handling
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Use SSI clock from master as SSI clock of slave.
2019-09-27 17:52:10 +03:00
994bb6d0cf
adaq7980: Software configurable trigger
2019-09-27 17:02:52 +03:00
b174333fa2
project-xilinx.mk: Clean generated file by sysid
2019-09-27 13:16:19 +03:00
7a685dd443
cn0506_rgmii/zcu102: Fix README typo
2019-09-26 16:33:45 +03:00
442b38033a
sys_id: added catch to git status check
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made error checking more general
2019-09-26 16:26:02 +03:00
447434ace0
cn0506_rgmii: Add support for a10soc
2019-09-20 18:03:27 +03:00
Laszlo Nagy
Adrian Costina
Istvan Csomortani
AndreiGrozav
Stanca Pop
Sergiu Arpadi
Stefan Raus
StancaPop