Commit Graph

591 Commits (e6d9735e54987b88d10003b43d0c285c4eabf546)

Author SHA1 Message Date
Adrian Costina d6163bea5e axi_jesd_gt: Fixed constraints 2015-06-10 10:56:22 +03:00
Adrian Costina 5e4f572092 axi_ad9122: Fixed constraints 2015-06-10 10:56:03 +03:00
Istvan Csomortani 4b08df9ed6 ad9361/tdd: Fix generation of tx_valid_* signals
In FDD mode the tx_valid_* signals are generated inside the axi_ad9361_tx module, in function of
the selected dac data rate. In TDD mode, these signals are gated by the tdd_enable and tdd_tx_dp_en signals.
In other words, the tx_valid_* signals will be valid just when tdd_enable and tdd_tx_dp_en is active.
2015-06-08 16:23:32 +03:00
Istvan Csomortani 2e877389b2 ad9361_tdd: Some naming and hierarchical changes 2015-06-04 18:09:49 +03:00
Istvan Csomortani 3b1ea7e528 axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch
598ece4c8d
2015-06-04 18:09:47 +03:00
Rejeesh Kutty 6548bcd71f axi_ip- constraints: add rst path 2015-06-04 10:53:13 -04:00
Rejeesh Kutty e02273781f ad_rst- non lpm version 2015-06-04 10:53:12 -04:00
Rejeesh Kutty 91b0f70972 library: remove drp cntrl 2015-06-02 09:58:57 -04:00
Adrian Costina 2b5abf74d7 util_upack: Show upack_valid only if the channel is activated 2015-06-02 11:36:06 +03:00
Rejeesh Kutty 297e885981 library- drp moved to up-clock domain 2015-06-01 14:52:52 -04:00
Rejeesh Kutty e7470036bf library- drp moved to up clock 2015-06-01 13:39:26 -04:00
Rejeesh Kutty c6ebab7393 library- drp moved to up clock 2015-06-01 13:39:26 -04:00
Rejeesh Kutty aa24c442f5 a10gx- no-ddr 2015-06-01 11:00:01 -04:00
Rejeesh Kutty d7b68c39ef altera- sdc 2015-06-01 10:59:59 -04:00
Rejeesh Kutty 2a0bdbebf2 altera- sdc 2015-06-01 10:59:58 -04:00
Rejeesh Kutty 92fc0e050d altera- common sdc 2015-06-01 10:59:57 -04:00
Adrian Costina 83df53d9bf adc_common: Updated version because the delay registers have been changed 2015-05-25 17:18:14 +03:00
Adrian Costina 1ef83bd88b axi_ad9671: Updated port names. Fixed synchronization of the rx_sof with the ad_jesd_align module, so that data valid is assigned correctly 2015-05-23 00:16:27 +03:00
Istvan Csomortani 660c84e01c axi_ad9434 : Update the IO delay interface 2015-05-22 19:47:09 +03:00
Rejeesh Kutty 0c6ef203c0 iobuf: do is a system-verilog keyword 2015-05-21 14:06:13 -04:00
Rejeesh Kutty dc2eeebf2f upack: gen-name 2015-05-21 14:06:12 -04:00
Rejeesh Kutty 5c6340e927 dmac: clock-typo 2015-05-21 14:06:11 -04:00
Rejeesh Kutty e05ff26406 ad9144: ddata-typo 2015-05-21 14:06:09 -04:00
Rejeesh Kutty 8d78217f7b ad9680: missing prot. ports 2015-05-21 14:06:08 -04:00
Rejeesh Kutty 4c6a3afc88 ad9144: missing prot. ports 2015-05-21 14:06:06 -04:00
Lars-Peter Clausen a059290cf5 Remove axi_ad7175
This core has been superseded by the SPI Engine framework in combination
with the axi_generic_adc core.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-21 17:21:35 +02:00
Lars-Peter Clausen c53f8c15ee Add CN0363 project
Add support for the CN0363 (colorimeter) board connected to the ZED board.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-21 17:21:35 +02:00
Lars-Peter Clausen d43ba44d0f Add util_sigma_delta_spi peripheral
The util_sigma_delta_spi peripheral can be used to seperate the interleaved
SPI bus and DRDY signals for a ADC from the Analog Devices SigmaDelta
family.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-21 17:21:35 +02:00
Lars-Peter Clausen e6b58e8a20 Add SPI Engine framework
SPI Engine is a highly flexible and powerful SPI controller framework. It
consist out of multiple sub-modules which communicate over well defined
interfaces. This allows a high degree of flexibility and re-usability while
at the same time staying highly customizable and easily extensible.

Currently included are four components:
	* SPI Engine execution module: The excution module is responsible for
	  handling the low-level physical interface SPI logic.
	* SPI Engine AXI interface module: The AXI interface module allows
	  memory mapped acccess to a SPI bus control stream and can be used to
	  implement a software driver that controls the SPI bus.
	* SPI Engine offload module: The offload module allows to store a
	  predefined SPI Engine command and data stream which will be send out
	  when a external trigger signal is asserted.
	* SPI Engine interconnect module: The interconnect module allows to
	  combine multiple control streams into a single stream giving multiple
	  control modules access to a execution module.

For more information see: http://wiki.analog.com/resources/fpga/peripherals/spi_engine

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-21 17:21:35 +02:00
Lars-Peter Clausen a5b452cc27 Add axi_generic_adc core
The axi_generic_adc core is a simple core that doesn't do much more then
implementing the AXI ADC register map and routing the enable and overflow
signals to the farbic.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-21 17:21:35 +02:00
Lars-Peter Clausen 033713ccb5 Add cordic demodulator module
The cordic_demod module takes in phase and data on s_axis interface then
performs a cordic demodulation and outputs the resulting I and Q component
data on the m_axis interface.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-21 17:21:35 +02:00
Lars-Peter Clausen cefbe3a0ff scripts/adi_ip.tcl: Add option to specify reset interface direction
Allow to specify the direction of the reset signal for a interface, this is
useful if the core itself generates the reset signal.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-21 17:21:35 +02:00
Lars-Peter Clausen 6b9906b22b Refresh Makefiles
Re-generate the Makefiles after a small update to the generation script:
- Entries are sorted alphabetically
- Empty dependency lines are skipped

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-21 14:21:54 +02:00
Adrian Costina 5ac7ebb8a3 axi_mc_*: Removed delay pins from up_adc_common 2015-05-21 14:03:58 +03:00
Rejeesh Kutty 465f7dff88 library/util_jesd_align -added 2015-05-20 15:38:43 -04:00
Rejeesh Kutty 9762c65868 library- jesd-align port name change 2015-05-20 14:25:21 -04:00
Rejeesh Kutty da0409b5a6 library- qsys components 2015-05-20 11:51:50 -04:00
Rejeesh Kutty 9b425736ac library: altera ip modifications 2015-05-20 10:41:21 -04:00
Rejeesh Kutty d48d3f4aa3 scripts/ip-alt- added 2015-05-20 09:11:18 -04:00
Rejeesh Kutty e918588a4b library: remove axi-min-size parameter 2015-05-19 13:07:48 -04:00
Rejeesh Kutty 4fb1be0672 ad9680: delay changes 2015-05-19 12:53:56 -04:00
Rejeesh Kutty af7afd7366 ad9671: delay changes 2015-05-19 12:53:56 -04:00
Rejeesh Kutty 09a05fe9d8 ad9652: delay changes 2015-05-19 12:53:56 -04:00
Rejeesh Kutty 13156593f8 ad9643: delay changes 2015-05-19 12:53:56 -04:00
Rejeesh Kutty c8d3c04a05 ad9625: delay changes 2015-05-19 12:53:56 -04:00
Rejeesh Kutty f53204f9f9 ad9467: delay changes 2015-05-19 12:53:56 -04:00
Rejeesh Kutty fe0ceb2530 delay-cntrl updates 2015-05-18 15:23:10 -04:00
Rejeesh Kutty 304a202d67 delay-cntrl updates 2015-05-18 14:57:05 -04:00
Rejeesh Kutty 2e257db109 delay-cntrl updates 2015-05-18 14:53:24 -04:00
Rejeesh Kutty 0877c252ad delay-cntrl changes 2015-05-18 14:28:20 -04:00