2dfcb0c599
usdrx1: Initial commit for a5gt
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axi_ad9671: added start of frame information to the altera core.
2014-10-07 19:41:54 +03:00
bfa17844ff
ad_serdes_in: General update
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Added a parameter for option SDR / DDR mode, added a parameter for parallel data width.
Note: default IF_TYPE is SDR and default PARALLEL_WIDTH is 8
2014-10-07 17:42:27 +03:00
de33722470
up/constr: independent read/write and local constraints
2014-10-02 14:35:59 -04:00
079ed0ffb3
ad_serdes_in: Update the serdes_in module
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Add additional IDELAY block before the ISERDES. Delet the IDDR blocks. Be aware, the ISERDES block are running in DDR mode. If the interface is SDR the maximum parallel data width is 4.
2014-09-25 16:40:29 +03:00
27ffff827a
common: Initial check in of ad_serdes_in.v
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A generic serdes module for input interface, support both 6 and 7 series.
2014-09-24 18:34:40 +03:00
5af2474d51
usdrx1: axi_ad9671 / axi_jesd_gt added signal for frame synchronization
2014-09-23 22:44:33 -04:00
b877cea2ed
up_axi: Add parameter to configure the internal address width
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Not all peripherals need 14 bit of address space.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-11 12:26:40 +02:00
41cc92ef49
Remove BASEADDR/HIGHADDR parameters
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This is unused and unneeded. The AXI interconnect will make sure that a
peripheral only gets requests that are meant for it, there is no need to
check the address in the peripheral itself.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-11 12:26:37 +02:00
6ad589475a
up_axi: Prevent read and write requests from racing against each other
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Make sure that if a read and a write request arrive on the very same clock
cycle to only accept one of them. The simple solution chosen here is to only
accept the write request when this happens and delay the acceptance of the
read request until the write request is finished.
This solution is not fair since a write request will always take precedence,
which in theory allows the write bus to starve the read bus. But in practice
we should never see that many write requests that we are unable to answer
the read request.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-10 13:04:05 +02:00
18a506b3ca
up_axi: Wait for the transaction to fully finish before releasing up_axi_access
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Wait for the master to accept the response for the current transaction
before we allow a new transaction to start.
This fixes problems in case the master is not ready to accept the response
when we make it available.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-10 13:03:52 +02:00
50faf0c53a
Remove executable flags from non-exectuable files
2014-09-09 15:05:06 +02:00
a773cc4992
usdrx1: updated project
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ad_jesd_align wasa updated to be able to work with frames that have more than 4 octets per frame
2014-09-01 15:18:39 +03:00
2b15c7313e
ad_dcfilter: Fix filter loopback
2014-08-12 14:42:10 +03:00
701dc96016
up_dac_channel: make iq cor coeff(s) tc
2014-07-24 10:10:24 -04:00
db1c931736
ad9625_plddr: PL DDR3 fixes
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- Modified the axi slave interface handler
- Increased the rfifo_mem input depth to prevent overflow
2014-07-23 19:34:44 +03:00
2955b9db78
fifo2s: flush if no request, c5soc: 14.0
2014-07-15 16:25:33 -04:00
e7d5d79e42
daq2/kcu105: gth up and running - as it is commit
2014-07-10 10:56:37 -04:00
a9992f02b0
fifo2s: bug fixes- on 64mhz dma clock
2014-07-08 16:57:44 -04:00
a388ccab0a
fmcomms2/c5soc: initial checkin
2014-07-02 14:56:00 -04:00
60dd14bcdb
a5soc: removed jtag master control
2014-07-01 12:27:37 -04:00
b6052773b7
added adc/dac gpio registers
2014-06-27 14:45:58 -04:00
6b3312bbf9
library: register map changes and for mathworks
2014-06-24 14:24:22 -04:00
d4be46cc17
library: register map changes and for mathworks
2014-06-24 14:23:56 -04:00
cf56a568c6
kcu105: GTH updates
2014-06-05 14:27:38 -04:00
842cd98b61
ad9361: adc loopback option
2014-05-27 12:15:02 -04:00
0cd43e34f5
dds: zero scale fix
2014-05-21 11:54:49 -04:00
3aed3ba71c
axi_ad9361: fmcomms5 changes
2014-05-19 12:41:12 -04:00
f3f8374c75
ad9671: 2lane version
2014-05-08 18:33:26 -04:00
5f2fb45b24
library: ported hdmi tx to altera
2014-05-02 12:07:47 -04:00
503096de18
gt: change userready on drp clock
2014-04-17 16:09:55 -04:00
c73390b6c9
axi_ad9361: Intermediary check in for altera porting
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This is work in progress. It will not work as it is
2014-04-11 17:40:34 +03:00
799d2384d8
up_xfer_cntrl: Remove extra semicolon
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Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-04-10 13:50:39 +02:00
f8f2684b7e
up_gt: eyescan delay bug fix
2014-04-02 16:45:41 -04:00
2472d61daf
ad_gt_es: status asserted early for latency
2014-04-01 15:06:51 -04:00
724bd70a06
altera additions and replacements
2014-04-01 11:18:10 -04:00
25f416e46f
dds output is reset if disabled
2014-03-31 10:01:49 -04:00
ad491e92ab
changed pcore version and made it local (top shouldn't override)
2014-03-14 12:02:16 -04:00
fd14607da5
mult instances: consistent naming style
2014-03-12 15:42:47 -04:00
7fc5b8ecd9
common: use dsp slice for multiply modules
2014-03-12 15:35:21 -04:00
0817973cc0
library: removed xilinx dc filter and dds
2014-03-10 14:52:48 -04:00
bb0431d3e8
library: dds and dcfilter changes, added fifo wrappers
2014-03-10 11:11:50 -04:00
d6256e9e29
library: dds and dcfilter changes, added fifo wrappers
2014-03-10 11:11:16 -04:00
23a62a92b2
up_adc_common: dma bus width is 0x8 (constant)
2014-03-06 19:22:19 -05:00
f7c9368abc
initial checkin
2014-02-28 14:26:22 -05:00
Adrian Costina
Istvan Csomortani
Rejeesh Kutty
Lars-Peter Clausen
U-ANALOG\ACostina