d7e87a60a9
Remove executable flag from non-executable files
...
All of these files are source code and are not executable standalone.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-28 17:56:07 +02:00
3eeba8273a
hdlmake.pl/fmcomms2- updates
2017-07-24 16:33:40 -04:00
eb113c8698
fmcomms2_kcu105: Initial commit
2017-07-24 18:45:48 +03:00
b7ca17f02b
scripts: Change adi_project_create to adi_project_xilinx for creating xilinx projects
2017-06-07 12:06:50 +03:00
491602d88b
make: Update make files
2017-06-06 12:00:40 +03:00
84b2ad51e2
license: Add some clarification to the header license
2017-05-31 18:18:56 +03:00
85ebd3ca01
license: Update license terms in hdl source files
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Fix a few gramatical error, fix the path of the top level license
files.
2017-05-29 09:55:41 +03:00
669e0a01d0
fmcomms2/a10gx: Remove project
2017-05-26 17:05:55 +03:00
4c998d1e18
make: Update make files
2017-05-25 15:12:17 +03:00
9055774795
all: Update license for all hdl source files
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All the hdl (verilog and vhdl) source files were updated. If a file did not
have any license, it was added into it. Files, which were generated by
a tool (like Matlab) or were took over from other source (like opencores.org),
were unchanged.
New license looks as follows:
Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
Each core or library found in this collection may have its own licensing terms.
The user should keep this in in mind while exploring these cores.
Redistribution and use in source and binary forms,
with or without modification of this file, are permitted under the terms of either
(at the option of the user):
1. The GNU General Public License version 2 as published by the
Free Software Foundation, which can be found in the top level directory, or at:
https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
OR
2. An ADI specific BSD license as noted in the top level directory, or on-line at:
https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
2017-05-17 11:52:08 +03:00
ebeebdddf0
altera- infer latest versions
2017-05-12 13:40:14 -04:00
bb0cdf2f5e
fmcomms2: Update IP instantiations
2017-04-21 15:09:37 +03:00
1d4b92190a
fmcomms2/zc702: Fix Warning[Synth 8-2611]
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In Verilog-2001 standard, redeclaration of an output port as a wire
is not allowed.
2017-04-19 13:54:03 +03:00
942d69a30c
Makefiles: Change MMU enabling parameter for altera designs from MMU to NIOS2_MMU
2017-04-18 10:57:16 +03:00
1c23cf4621
all: Update verilog files to verilog-2001
2017-04-13 11:59:55 +03:00
7e87ecae22
altera/a10gx- daq1/fmcomms2 fix typos
2017-03-22 09:48:02 -04:00
8063ba2b66
make updates
2017-03-20 16:05:18 -04:00
9b6dd27c23
ad9361- delay initialization
2017-03-15 12:06:59 -04:00
c3c8c366d3
axi_ad9361- add receive init delay
2017-03-13 16:28:53 -04:00
0ae79ca7ac
move/rename - delay script belongs to ad9361
2017-03-10 12:44:32 -05:00
452e5e5ce0
fmcomms2- add delay reporting for iodelay
2017-03-09 15:29:15 -05:00
8bdfbe2b0a
fmcomms2- report delays
2017-03-09 15:21:42 -05:00
c598e84258
remove processing order (no clock def dependency)
2017-02-22 16:02:08 -05:00
8a5e2ff46e
sys_wfifo- removed
2017-02-22 15:13:18 -05:00
58872aa3ef
fmcomms2/zc706pr- prcfg is a single clock synchronous design
2017-02-06 10:59:18 -05:00
48ad24cdbe
enable partial reconfiguration mode
2017-01-27 09:26:53 -05:00
4dcad7e116
fmcomms2: zcu102, update clkdiv device parameter
2017-01-16 14:38:37 +02:00
a36057679a
fmcomms2: Update Makefiles
2017-01-13 14:16:21 +02:00
15c5bc7012
fmcomms2: zcu102, changed clkdiv C_SIM_DEVICE parameter to ultrascale
2017-01-13 13:57:32 +02:00
b84325d43f
fmcomms2: take into consideration both adc_r1 and dac_r1 for clock division selection
2017-01-13 13:56:04 +02:00
e77428c50e
fmcomms2: Added FIFOs for DAC and ADC paths so that the path works at l_clk / 2 or l_clk /4
...
- removed ILA
2017-01-11 18:12:35 +02:00
4a783d523d
projects/altera* - default & common qsys commands
2016-12-20 16:27:44 -05:00
8ebc8fe4e2
updated makefiles
2016-12-09 23:06:41 +02:00
b0eff57b0f
fmcomms2/zc702: Fix critical warnings
2016-12-08 19:54:52 +02:00
170c781d02
hdlmake.pl- updates
2016-12-01 13:52:11 -05:00
69ee410d3d
fmcomms2/zc706pr- bypass pr as default
2016-11-21 09:45:10 -05:00
1cbea90bac
altera - a10gx bank swap
2016-11-01 12:41:25 -04:00
1e0fed82f7
alt_serdes- a10 ddio fixes
2016-11-01 12:41:25 -04:00
671a547c2b
hdlmake- updates
2016-11-01 12:41:25 -04:00
7b958fed87
hdlmake- updates
2016-10-21 13:59:43 -04:00
17cfdd6be9
fmcomms2/a10gx: Update Makefile and qsys script
2016-10-18 12:42:14 +03:00
cb97bc500a
hdlmake updates
2016-10-17 16:29:57 -04:00
905e29eb01
hdlmake- altera
2016-10-10 12:55:55 -04:00
8e1034946f
fmcomms2/zcu102- 2016.2 updates
2016-09-30 11:55:10 -04:00
f1e787f86b
fmcomms2: TDD control is enabled by default
2016-09-16 14:45:39 +03:00
16ee1336c3
Makefile: Update make files
2016-09-15 11:41:06 +03:00
f697490de6
hdlmake- updates
2016-08-19 15:59:41 -04:00
0b0aa8e6c0
Makefile: Add MMU option to altera makefiles
2016-08-11 17:46:54 +03:00
0cd608a7e2
lib_refactoring: Update Make files
2016-08-08 16:38:38 +03:00
df36902713
lib_refactoring: Fix path of the IO macros
2016-08-08 15:07:19 +03:00
d60bce654c
Makefiles: Updated Makefiles so they run correctly with gnuwin32 tools
2016-08-05 15:16:04 +03:00
e42b4ea378
hdlmake- updates
2016-08-04 13:28:25 -04:00
7ca8e10004
make: Update Make files
2016-08-01 14:24:48 +03:00
af4c43b6e1
hdl-vivado-2016.2: Update fmcomms2 and pzsdr base design
2016-08-01 13:49:12 +03:00
39a5534e00
hdlmake- updates
2016-07-21 16:10:38 -04:00
12abe2b6b9
fmcomms2: Makefile update
2016-07-12 09:39:24 +03:00
283bf9ad75
fmcomms2_a10GX: Add fmcomms2 on a10gx
2016-07-11 18:37:18 +03:00
e9fe752b7a
fmcomms2_qsys.tcl: Add fmcomms2 block design script for Altera
2016-07-11 18:34:21 +03:00
48762519b5
make updates
2016-07-06 15:02:00 -04:00
67c948e821
fmcomms2/a10soc-- bad board design
2016-06-14 12:29:36 -04:00
eaf4d4a19d
makefile updates
2016-06-10 14:26:14 -04:00
09520709b0
make updates
2016-05-20 12:35:45 -04:00
e1350018da
zcu102- updates
2016-05-10 15:40:41 -04:00
a6411dbd63
zcu102- added
2016-05-10 15:40:41 -04:00
8d72b645ae
fmcomms2/common: Remove ila_tdd block
2016-05-09 10:28:10 +03:00
ddfaff2cf5
fmcomms2/a10soc: compile version
2016-05-04 13:42:12 -04:00
f4e5965936
fmcomms2/a10soc: ip updates
2016-05-04 13:42:12 -04:00
385ed31a45
make files update
2016-04-29 10:17:35 -04:00
61b531b1c1
a10soc device update
2016-04-29 10:17:35 -04:00
e790e4c3ae
a10soc- complete qsys
2016-04-25 12:56:19 -04:00
bfa6fe2a40
a10soc- updates
2016-04-25 11:23:16 -04:00
28159aeec9
a10soc- updates
2016-04-25 11:11:46 -04:00
0a3967b886
a10soc- updates
2016-04-25 10:53:26 -04:00
d36d1263c5
a10soc- updates
2016-04-25 10:50:09 -04:00
2a5f31d26b
fmcomms2/a10soc- copy
2016-04-22 15:15:44 -04:00
679d471d75
Merge branch 'hdl_2016_r1' into dev
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hdl_2016_r1 contains IP core upgrades to Vivado 2015.4.2 and hdmi_tx improvements.
2016-04-19 18:05:50 +03:00
3006c5a223
make updates
2016-04-11 16:14:59 -04:00
21208ca208
Makefiles: Update Makefiles
2016-03-31 12:37:47 +03:00
995debedce
fmcomms2: Update common design to 2015.4
2016-03-18 15:26:52 +02:00
ceea7f25b2
fmcomms2: Updated common design to 2015.4
2016-03-15 15:23:20 +02:00
e381d5170c
util_tdd_sync: Update the synchronization interface
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Simplify the synchronization interface, there is one signal line between the synchronization module and transceiver core.
2016-02-12 14:27:37 +02:00
c051a578e5
fmcomms2: Delete unnecessary clock definition
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The two clocks, rx_clk and ad9361_clk, are the same.
2015-11-20 19:35:37 +02:00
2345d29663
fmcomms2: Update make files
2015-11-11 11:15:45 +02:00
a936ad607f
fmcomms2/zc706: Delete unused files from file list
2015-11-11 11:14:58 +02:00
c7e86528d6
fmcomms2/zc706: Cosmetic changes on constraints file
2015-11-11 11:14:16 +02:00
6197a82c80
fmcomms2/common: Add the util_tdd_sync module
2015-11-11 11:07:15 +02:00
9d2b8809df
Makefiles: Updated Makefiles
2015-10-23 10:44:27 +03:00
21737ad7b8
fmcomms2/zc706pr: Update the fifo interface of the PR module
2015-10-13 11:37:44 +03:00
c9a5057b93
library/prcfg : Split data bus to channels
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Because of the new pack/upack modules on the data path, it makes more sense to split the data interface of the PR modules into separate channels.
The top module will supports max 4 channels.
2015-10-13 11:36:45 +03:00
c83239b014
fmcomms2/zc706pr: Update PR design
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+ Add system_top.v to design
+ Add pr specific constraints
2015-10-09 13:23:42 +03:00
f77f928444
fmcomms2/zed: Fix the system_top
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Fix the enable/txnrx control line.
2015-09-25 19:11:41 +03:00
aeb1d7aa3e
fmcomms2/zed: Cosmetic changes
2015-09-25 19:11:39 +03:00
f8b3096bd0
fmcomms2/vc707: Fix the system_top
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Fix the enable/txnrx control lines.
2015-09-25 19:11:37 +03:00
2c75cfd04e
fmcomms2/vc707: Cosmetic changes
2015-09-25 19:11:35 +03:00
ffa0bcd19f
fmcomms2/mitx045: Fix the system_top
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Fix the enable/txnrx control lines.
2015-09-25 19:11:32 +03:00
28d20e84c5
fmcomms2/zc702: Fix the system_top
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Fix the enable/txnrx control lines.
2015-09-25 19:11:30 +03:00
ea74413125
fmcomms2/kc705: Fix the system_top.
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Fix the enable/txnrx control lines.
2015-09-25 19:11:28 +03:00
f80622b972
fmcomms2/ac701: Fix the system_top
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Fix the enable/txnrx control line.
2015-09-25 19:11:26 +03:00
cd8b467b1e
fmcomms2: Drop explicit axi_dmac clock synchronicity configuration
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The axi_dmac core is now capable of detecting whether its different parts
run in different clock domains or not. No need to configure it manually any
more.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:28:07 +02:00
a679251d7d
Makefiles: Update Make
2015-09-09 17:13:19 +03:00
Lars-Peter Clausen
Rejeesh Kutty
AndreiGrozav
Adrian Costina
Istvan Csomortani