This will allow building base test harnesses and place on top of them
existing block designs for simulation purposes.
Test harnesses will contain basic functionality like
- clock and reset generators
- AXI master to aid register access of the cores.
- memory model of the DDR
- interrupt controller
Existing procedures (ad_mem_hp0_interconnect, ad_cpu_interconnect, ... ) will
connect to this harness as they do to a real base design.
To support deterministic latency with non-power of two octets per frame
(F=3,6) the interface width towards the transport layer must be resized
to match integer multiple of frames.
e.g Input datapath width = 4; Output datpath width = 6;
for F=3 one beat contains 2 frames
for F=6 one beat contains 1 frame
The width change is realized with a gearbox.
Due the interface width change the single clock domain core is split
in two clock domains.
- Link clock : lane rate / 40 for input datapath width of 4 octets 8b10b
- lane rate / 20 for input datapath width of 8 octets 8b10b
- lane rate / 66 for input datapath width of 8 octets 64b66b
- Device clock : Link clock * input data path width / output datapath width
Interface to transport layer and SYSREF handling is moved to device clock domain.
The configuration interface reflects the dual clock domain.
If Input and Output datapath width matches, the gearbox is no longer
required, a single clock can be connected to both clocks.
In most of the standalone projects the generic project creation flow is not followed. The project's device
is defined manualy. This fix makes sure that those projects still builds without an issue.
NOTE: In these case we should use adi_project_create directly in system_project.tcl.
Without defining this signal, the UART lines receive garbage data
when no cable is connected to the J4 USB UART port.
The GPIO9 is enabled in the reference base design along with the
4MA CURRENT_STRENGTH constraint on the UART pins
When phase alignment is active, the PFD frequency value should be used
as outclk1 actual frequency.
The configuration interface of the fPLL does not support fractional values.
If the reference clock is fractional, the tool will throw an error that requirement
above is not respected.
Round up the reference clock for the SERDES and the lane rate in order to
overcome this issue, until it's not fixed by Intel.
When phase alignment is active, the PFD frequency value should be used
as outclk1 actual frequency.
The configuration interface of the fPLL does not support fractional values.
If the reference clock is fractional, the tool will throw an error that requirement
above is not respected.
Round up the reference clock for the SERDES and the lane rate in order to
overcome this issue, until it's not fixed by Intel.
When phase alignment is active, the PFD frequency value should be used
as outclk1 actual frequency.
The configuration interface of the fPLL does not support fractional values.
If the reference clock is fractional, the tool will throw an error that requirement
above is not respected.
Round up the reference clock for the SERDES and the lane rate in order to
overcome this issue, until it's not fixed by Intel.
-change the video memory interfacing from f2h_axi_slave to
f2h_sdram0
- add f2h_sdram1 port as the default interface for converter DMA
- set as default the full HD resolution at 60 FPS (pixel clock 148.5MHz)
- use a second 200MHz(198MHz) clock from the pixel_clk_pll, as DMA source
to destination clock.
Also modified the FIFO ports to have the same widths so that in a
future commit the bypass would be available for cases when the
sampling rate won't be the maximum rate or the number of channels
active will be less than maximum number of channels
Switch RX path reset to be controlled by the TPL and use
RX SYSREF as external synchronization for the ADC TPL
Use TX SYSREF for synchornizing the TX DDS
The device clocks are AC coupled LVDS lines without external termination.
For proper operation internal differential termination must be enabled,
the DQS_BIAS will DC bias the AC coupled signal to VCCO/2 (1.8/2) 0.9V
Added reference design for the ad9656 evaluation board coupled with the
zcu102 carrier board. The JESD204 communication link that transfers data
from the 4 ADCs to the FPGA has the following paramenters : L=4, M=4, S=1,
F=2, HD=0, N=16, NP=16. The JESD204 line rate is configured to be 2.5GHz.
Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
The coraz7s has an Arduino/chipKIT Shield connector with 6 Single-ended
and 8 Differential Analog inputs tied to Xilinx's XADC.
The CN0540 uses the A0-5 pins as single-ended ADC channels to monitor
the differential input, ADC driver, and buffer voltages.
Signed-off-by: Sergiu Cuciurean <sergiu.cuciurean@analog.com>
Note, the current SCLK to spi_clk ratio is four. That means, the input
delay in the MISO line is 25% of the SCLK period.
If the SCLK to spi_clk ratio is changing, this constraint must be
updated.
Generate a higher frequency of spi_clk using an axi_clkgen. (MMCM)
CAUTION: ad7768-1 is still violating the standard SPI timing,
reducing the timing window significantly for the last bit (or last high
bit).
Ignore the following critical warning on DMAC instance:
Critical Warning (15003): "mixed_port_feed_through_mode" parameter of RAM atom
system_bd:i_system_bd|axi_dmac:axi_dmac_0|axi_dmac_transfer:i_transfer| \
dmac_request_arb:i_request_arb|dmac_dest_mm_axi:i_dest_dma_mm| \
altsyncram:bl_mem_rtl_0|altsyncram_0tp1:auto_generated|ram_block1a1
cannot have value "old" when different read and write clocks are used.
Due to the interface differences between HPS's AXI4 and DMA's AXI4, the
tool will try to automaticaly add some bridges between the two
interface. Unfortunatly it does generate timing issues at the f2sdram0
interface of the HPS instance. By explicitly instantiating an AXI
bridge, these timing issues disappears.
The reconfiguration interface for the Stratix10 XCVR has a different
address width. Prepare the register map layout of the project to support
this new architecture.
If we have a lot of peripherals connected to the CPU's memory interface,
the generated interconnect can grow to much decreasing the timing
margin.
One solution is to group the peripherals by its interface types and
functions and use bridges to connect them to the memory interface.
This commit adds the possibility to insert an Avalon Memory Mapped
bridge when we create the connection between the peripheral and CPU.
Should be used just with Avalaon Memory Mapped interfaces.
The ADRV9002 uses in the digital interface 1.8V, however the Zed VADJ is
selectable by a jumper can go up to 3.3V . Voltage levels higher than 1.8V
are detected by the EVAL-ADRV9002 board, asserting the VADJ_ERR pin.
If VADJ error is set high keep all drivers in high-z state and signalize
it to the software layer through a gpio line.
All input and output delays should be referenced to a virtual clock.
If the input and output delays reference base clocks or PLL clocks rather than
virtual clocks, the intra- and inter-clock transfer clock uncertainties,
determined by derive_clock_uncertainty, are incorrectly applied to the I/O ports.
See mnl_timequest_cookbook.pdf for more info.
By defualt the supported tool chain is Quartus PRO. If you want to
build the project with Quartus Standard, you need to define an environment
variable called QUARTUS_PRO_ISUSED with the value 0. (e.g. export
QUARTUS_PRO_ISUSED=0 )
Note: Not all projects going to build on Quartus Standard, you should
fix the errors if there is any.
There is a major compatibility issue between 2019.1 and 2019.2.
The file system_top.hdf got a different file extention. This will
cause a compilation failer in the end of the build. To save time
and fail earlier, upgrade the version mismatch message to ERROR.
If user still wants to build a branch with different tool version
the variable ADI_IGNORE_VERSION_CHECK should be set to 1.
On the Xilinx PHY the available PLL options depends on the lane rate.
Encoding is:
0 - CPLL
1 - QPLL0
2 - QPLL1
Since the selection of line rate is available from the project also the
PLL selection must be exposed.
The AFE's I2C interface should be pin-multiplexed to the FPGA. Also, add
a bidirectional IO buffer for the interface, and make sure it has weak
pull-up resistors.
Use over-writable parameters from the environment.
e.g.
make JESD_MODE=64B66B RX_RATE=24.75 TX_RATE=12.375 REF_CLK_RATE=375 RX_JESD_L=4 TX_JESD_L=4
make JESD_MODE=64B66B RX_RATE=16.22016 TX_RATE=16.22016 REF_CLK_RATE=245.76 RX_JESD_M=8 RX_JESD_L=2 TX_JESD_M=16 TX_JESD_L=4
make JESD_MODE=8B10B RX_JESD_L=4 RX_JESD_M=8 TX_JESD_L=4 TX_JESD_M=8
The previous mechanism was "probing" the DMAs for valid data. Better said,
each interpolation channel enabled it's DMA until a valid data was received,
then it disabled the DMA read and waited for the adjacent channel(DMA) to
receive a valid data. Only when for both channels had valid data on the
DMAs interfaces was the transmission started. This added an undesired and
redundant complexity to the interpolation channels. Furthermore, for continuous
transmission, using the above mechanism lead to a fixed phase(sample)
shift between the two channels at each start.
By using the streaming mechanism the interface is simplified and the
above problems are solved.
Because fmcomms2 was not supported on a Intel carriers the
fmcomms2_qsys.tcl file got outdated.
The arradio project has the same hdl design. Hence the update is
merely a copy of the arradio_qsys.tcl with small changes.
This commit fixes the critical warning regarding the missing clock
definitions.
- Defined MDC(MDIO) clocks
- Set false path on(to) the ps8 MDIO input pins. There are synchronization
stages in the GMII to RGMII converter for the CDC between the 375M refclk
and 2.5M MDC clock domains.
implemented mux for temp reading either from internal or external
source; updated regmap; added param to identify source for temp
information; updated tacho measurements; added AVG_POW param used
for tacho measuremet average useful for simulations; defaults for
tacho measurements changed to params and added registers; added
prescaler for fsm control, FSM updated; changed register write
process; connected INTERNAL_SYSMONE to regmap, value can now be
read by software;
Because of the rmii mode requirements(external 50MHz clock) the
board will have the rx_err signal replaced on the FMC connector with the
50MHz external clock (D08/D20).
The rx_er will be shifted to the D9/D21 pins.
The IO location of the laser_driver_otw_n was moved from FMC_HPC_LA27_N
to FMC_HPC_LA31 (laser_gpio[12]).
laser_gpio[11:0] assignments were shifted with one bit to MSB, and laser_gpio[0]
got the old location of the laser_driver_otw_n.
When channels are not swapped in groups of four but are completely out of order
the common control channel can't be reordered based on the index of the
channel.
The DDR controller for C2 for is much closer to the transceivers which
connect to the FMCp connector so designs does not have to span over all
three SLRs just over two reducing implementation and timing closure effort.
stefan.raus
Laszlo Nagy
Sergiu Arpadi
Adrian Costina
Istvan Csomortani
aholtzma
AndreiGrozav
IMoldovan
hotoleanudan
Sergiu Cuciurean
Stanca Pop
Stanca.Pop
Dragos Bogdan
StancaPop
István Csomortáni
Prasahnt Sivarajah