Commit Graph

1696 Commits (e754f0a46a94a7ce9d139fbb0140ecb1094e4ee9)

Author SHA1 Message Date
Dragos Bogdan 39c1c83d00 adrv9371x/a10soc: Fix spi_csn assignment 2016-08-12 10:07:11 +03:00
Adrian Costina 0b0aa8e6c0 Makefile: Add MMU option to altera makefiles 2016-08-11 17:46:54 +03:00
Rejeesh Kutty 5d93e542ed daq2-kcu105: 2016.2 updates 2016-08-11 10:00:41 -04:00
Rejeesh Kutty 16ad0f4379 kcu105- 2016.2 update 2016-08-11 10:00:41 -04:00
Adrian Costina 285059aed0 kcu105: Don't use phy reset automation, as it's not supported for KCU105 2016-08-09 10:19:57 +03:00
Adrian Costina 452d4706d3 kcu105: Update base project to 2015.4.2
- change part to revision 1.1 of the board
2016-08-09 10:19:36 +03:00
Rejeesh Kutty c6f4def93d altera- make mmu a make switch 2016-08-08 11:54:51 -04:00
Istvan Csomortani 0cd608a7e2 lib_refactoring: Update Make files 2016-08-08 16:38:38 +03:00
Istvan Csomortani df36902713 lib_refactoring: Fix path of the IO macros 2016-08-08 15:07:19 +03:00
Istvan Csomortani f784557895 lib_refactoring: IOBUF is a Xilinx macro, no need to use with Altera 2016-08-08 15:06:34 +03:00
Lars-Peter Clausen 8f61e11a70 pzsdr: ccpci: Add PCIe reset monitor
For reliable and correct operation it is vital that the FPGA is fully
configured and up and running before the PCIe host de-asserts the reset.

Add a small logic circuit that detects de-assertion of the reset signal
that can be used to verify that the reset de-assertion was seen by the
FPGA.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-08-05 18:31:40 +02:00
Lars-Peter Clausen 91782989ad pzsdr: ccpci: Set IO standard to LVCMOS33 for banks 12 and 13
The IO voltage for bank 12 and 13 is 3.3V on the PCIe carrier. Set the
IOSTANDARD of the pins on these banks accordingly.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-08-05 18:31:40 +02:00
Lars-Peter Clausen 418217dd10 pzsdr: Remove LED and button signals from PCIe carrier
Only the FMC carrier and the breakout board do have push buttons and LEDs.
They are not present on the PCIe carrier. So move the constraints to a
separate file that can be included by the projects that need them and
remove all LED and button related signals from the PCIe project.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-08-05 18:31:40 +02:00
Lars-Peter Clausen 3cff0fa7dc pzsdr: ccpci: Use PL SPI and GPIO peripherals
To be able to access the GPIO pins and the SPI port through the PCIe bridge
we need to use the PL SPI and GPIO controllers rather than the PS
controllers. Adjust the sytem_top.v accordingly so that the PL peripherals
are connected to the external pins.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-08-05 18:29:42 +02:00
Adrian Costina d60bce654c Makefiles: Updated Makefiles so they run correctly with gnuwin32 tools 2016-08-05 15:16:04 +03:00
Rejeesh Kutty e42b4ea378 hdlmake- updates 2016-08-04 13:28:25 -04:00
Rejeesh Kutty ed9e92621c daq2- spi+xcvr address conflict 2016-08-04 10:50:31 -04:00
Adrian Costina 999eccc134 daq3: Update A10GX project to Quartus 16.0 2016-08-01 16:19:43 +03:00
Adrian Costina 9a563de8ff daq2: A10GX updated project to Quartus 16.0
- connected directly axi_ad9680 to xcvr_core, skipping axi_jesd_xcvr
2016-08-01 15:09:53 +03:00
Adrian Costina 52ae3ddd6c a10gx: Updated common files to 16.0 2016-08-01 15:08:12 +03:00
Istvan Csomortani 7ca8e10004 make: Update Make files 2016-08-01 14:24:48 +03:00
Istvan Csomortani af4c43b6e1 hdl-vivado-2016.2: Update fmcomms2 and pzsdr base design 2016-08-01 13:49:12 +03:00
Istvan Csomortani fbe3d75eb0 cosmetics: Delete trailing whitespace characters 2016-08-01 13:46:46 +03:00
Shrutika Redkar 9952a94efb hdl-vivado-2016.2- ip version updates 2016-07-28 13:44:57 -04:00
Shrutika Redkar 6ffe59728b hdl-vivado-2016.2- update 2016-07-28 13:44:57 -04:00
Shrutika Redkar 3b2bde2fa1 hdl-vivado-2016.2- min. addr-space requirement 2016-07-28 13:44:57 -04:00
Adrian Costina 08f4ba24d5 usb_fx3: Switch PS7 UART to UARTLITE to communicate with the FX3 board 2016-07-28 15:21:38 +03:00
Rejeesh Kutty 39a5534e00 hdlmake- updates 2016-07-21 16:10:38 -04:00
Rejeesh Kutty 6df5ba1a7a daq2- adxcvr version 2016-07-21 16:09:33 -04:00
Rejeesh Kutty 4532e5c0cb fmcomms11- support iq mode 2016-07-21 11:58:03 -04:00
Rejeesh Kutty c75289be21 fmcomms11- use qpll tx-12g5, cpll rx-6g25 2016-07-19 16:21:49 -04:00
Shrutika Redkar d6243f3d01 update in fmcomms11 tcl and clock constrains 2016-07-18 09:04:13 -04:00
Lars-Peter Clausen 44d9f98e12 adi_project.pl: Fix ADI_NO_BITSTREAM_COMPRESSION detection logic
Only enable bitstream compression only if both the
ADI_NO_BITSTREAM_COMPRESSION environment and TCL variable are not set.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-07-14 10:44:42 +02:00
Lars-Peter Clausen 62c7114d77 Enable bitstream compression for Xilinx projects
Enabling bitstream compression reduces the size of the generated bitstream.

This means on one hand it will consume less storage, which is especially
useful for the BOOT partition of the ADI images where we store BOOT.BIN
files for all supported platforms.

On the other hand a smaller bitstream is faster to load from the storage
medium and it is also faster to program to the FPGA. So it reduces the
overall boot time as well.

The only downside of bitstream compression is that the bitstream size is no
longer constant, but depends on the actual design and resource utilization.
This will not work with bootloaders that expect a fixed size.

When building a bitstream using the tcl scripts bitstream compression can
be disabled by setting the ADI_NO_BITSTREAM_COMPRESSION environment
variable.

Initial tests show a reduction of a round 50% in size for most ADI
projects.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-07-14 10:16:15 +02:00
AndreiGrozav 12abe2b6b9 fmcomms2: Makefile update 2016-07-12 09:39:24 +03:00
AndreiGrozav 283bf9ad75 fmcomms2_a10GX: Add fmcomms2 on a10gx 2016-07-11 18:37:18 +03:00
AndreiGrozav e9fe752b7a fmcomms2_qsys.tcl: Add fmcomms2 block design script for Altera 2016-07-11 18:34:21 +03:00
Adrian Costina 92c580a84d daq3: A10GX, updated project to the TCL flow 2016-07-08 12:00:37 +03:00
Istvan Csomortani 7be017baa3 daq1: Add AXI PLDDR FIFO to the receive path
The AD9684 has two 500 MSPS converter, the system can not handle this
throughput without a FIFO.
2016-07-07 07:15:54 +03:00
Istvan Csomortani 9169e20b5e daq1: Fix the data width on the DMAC interfaces
+ HP ports maximum width is 64 bits
+ DMAC's default width is 64, no need for redefinition
2016-07-07 07:15:54 +03:00
Rejeesh Kutty 48762519b5 make updates 2016-07-06 15:02:00 -04:00
Istvan Csomortani 427cc84bb2 axi_ad7616: Rename the physical interface signals to rx_*
No functional modification.
2016-07-01 14:45:23 +03:00
AndreiGrozav 69a68a99e0 imageon/zed - remove onboard hdmi and update design 2016-07-01 14:11:49 +03:00
Shrutika Redkar ad491ec04a updated tcl files after inclusion of ad9162 core 2016-06-30 13:26:16 -04:00
Adrian Costina c6c3622816 a10gx: Updated common design adding explicit clock frequency and synchronous reset deassertion 2016-06-30 10:59:29 +03:00
Istvan Csomortani 8d558b2538 make: Update Make files 2016-06-29 14:50:07 +03:00
Istvan Csomortani e6494b9a74 axi_ad7616: Change the DMA interface type to Write FIFO 2016-06-29 14:11:02 +03:00
Istvan Csomortani 64633e519c Merge remote-tracking branch 'origin/dev_ad7616' into dev 2016-06-29 12:32:39 +03:00
Istvan Csomortani 2e80dec513 adrv9371x/zc706: Update project with the new axi_dacfifo 2016-06-22 12:33:47 +03:00
Rejeesh Kutty 67c948e821 fmcomms2/a10soc-- bad board design 2016-06-14 12:29:36 -04:00