Commit Graph

25 Commits (e757859b56f4a15b8c99c68f48b36ac5cd96ca11)

Author SHA1 Message Date
AndreiGrozav 7e84c2575c axi_pwm_gen: Fix 100% duty cycle width
Signed-off-by: AndreiGrozav <andrei.grozav@analog.com>
2024-04-30 15:28:14 +03:00
AndreiGrozav 8c08c5a65a axi_pwm_gen: Update constraint file
This change will fix the timing closure for designs where the external
clock is not a submultiple of the s_axi_clk.

Signed-off-by: AndreiGrozav <andrei.grozav@analog.com>
2024-04-19 15:23:55 +03:00
AndreiGrozav 344ca6fc3d axi_pwm_gen: New features and fixes
New features:

1. External sync force the phase align. The external sync was used to align
   the phases of enabled pwms, but only after being armed by a
   load_config signal toggle.
   This feature lets the user decide between using load_config to
   arm and wait for a neg-edge of sync or automatic phase align trigger
   on the ext_sync neg-edge.
2. Force align. Lets the user chose between immediately stopping the
   active pulses and realigning them, or waiting for all running pulse
   periods end, before realigning.
3. Start at sync. When this feature is activated, the pulses will start immediately
   after the trigger event. Otherwise, each pulse will start after a period
   equal to the one for which it is set.
4. Use parameters to set the default status after reset of the
   - soft reset
   - start at sync
   - force align
   - ext sync align

Update regmap.

Fixes:

1. The polarity on disabled channels was staying high instead of low.
2. Fix 0 and 100 proc duty cycle configuration.

Signed-off-by: AndreiGrozav <andrei.grozav@analog.com>
Signed-off-by: Alin-Tudor Sferle <Alin-Tudor.Sferle@analog.com>
2024-04-19 15:23:55 +03:00
Villyam fd81a821b0 library/axi_pwm_gen: Replaced blocking assignments in reset.
Lattice tools give error for using blocking assignments at one side
and non blocking in the other.

Signed-off-by: Villyam <Vilmoscsaba.Jozsa@analog.com>
2024-03-28 17:16:04 +02:00
PIoandan 86cd484865
lib/axi_pwm_gen: Update pause_cnt logic (#1271)
Signed-off-by: Ioan-daniel Pop <Pop.Ioan-daniel@analog.com>
2024-02-07 11:16:40 +02:00
Iulia Moldovan 68461110aa Replace link in license header from master to main
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2024-01-16 16:48:45 +02:00
AndreiGrozav 870b27d3d3 axi_pwm_gen: Update ttcl constraints
Signed-off-by: AndreiGrozav <andrei.grozav@analog.com>
2023-12-15 15:03:07 +02:00
AndreiGrozav e0fc09fc9e axi_pwm_gen: Start, Stop fix
Previously when issuing a load_config, each pwm channel
was stopped in its tracks and waited for an external sync,
if that was active, or load_config release.
The desired behaviour is to wait for the pwm channels to finish
their events from the current period, before a new aligned start.
Also, the first positive edge of each pulse was initiated only
in the second pwm channel period.
This niche behaviours have not affected any functionality in the
long term alignments for current setups.

Signed-off-by: AndreiGrozav <andrei.grozav@analog.com>
2023-12-15 15:03:07 +02:00
AndreiGrozav e7dd5ce394 axi_pwm_gen: Offset mecanism fix
When leaving the offset equal to zero for a pwm
channel. That pwm channel was not waiting for all
channels to get in sync after a load config.

Signed-off-by: AndreiGrozav <andrei.grozav@analog.com>
2023-12-15 15:03:07 +02:00
Alin-Tudor Sferle 119d4e43a3 axi_pwm_gen: Add support for 16 channels
Signed-off-by: Alin-Tudor Sferle <Alin-Tudor.Sferle@analog.com>
Signed-off-by: AndreiGrozav <andrei.grozav@analog.com>
2023-12-15 15:03:07 +02:00
Iulia Moldovan c9a7d4d927 Add copyright and license to .tcl, .ttcl files
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-07-25 15:22:26 +03:00
Iulia Moldovan 27bb69b44c Add copyright and license to .sdc files
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-07-25 10:41:40 +03:00
Iulia Moldovan 28c06d505f Add/edit copyright and license for .v, .sv files
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-07-11 15:17:41 +03:00
Sergiu Arpadi 369e34425f axi_pwm_gen: Update timing constraints, hw.tcl and sdc files.
Not using util_cdc_constr.tcl
2023-03-30 14:55:59 +03:00
laurent-19 83284107a2 library/axi_pwm_gen: Assign correct reg value to offset_0
Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
2023-03-22 17:58:18 +02:00
Jem Geronimo 2db944396f
axi_pwm_gen: add: intel support (#1080)
Signed-off-by: Jem Geronimo <johnerasmusmari.geronimo@analog.com>
2023-02-07 18:27:04 +08:00
Iulia Moldovan db94628cc6 library & projects: Update Makefiles
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-01-27 11:54:05 +02:00
Iacob_Liviu 482f0489a3 scripts: Merge adi_env.tcl into a single file
Move the new adi_env.tcl file from hdl/projects/scripts into hdl/scrips
2022-08-08 13:52:54 +03:00
Iulia Moldovan 0c0617d49e libraries: Update modules according to guideline
* Added header license for the files that didn't have
* Modified parentheses
* Removed extra spaces at the end of lines
* Fixed parameters list to be each parameter on its line
* Deleted lines after endmodule and consecutive empty lines
* Fixed indentation

Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
2022-06-28 18:06:56 +03:00
Nick Pillitteri c1721e18dd account for ADI_VIVADO_IP_LIBRARY global variable when adding subcores 2022-03-24 16:29:49 +02:00
LIacob106 076e81a17c library: Add link to wiki for IPs 2021-10-25 10:44:53 +03:00
AndreiGrozav 76cd5581bc axi_pwm_gen: Add config in soft reset option 2021-09-17 11:50:46 +03:00
Adrian Costina 591a23156b Makefiles: Update header with the appropriate license 2021-09-16 16:50:53 +03:00
AndreiGrozav 81320b6469 axi_pwm_gen: Fix offset mechanism
Fix offset for pwms with different periods.
The previous version was using an offset scheme based on pwm counter_0.
By using a separate offset counter the user will not be constrained by
pwm_0 period in regards with the offset of other pulses. In this version
offset 0 is used to delay pwm 0 in regards to the offset counter.

The offset counter will start after the load_config signal is asserted
and all active pwm counters finish the previous cycle or by a software
reset.

The software reset should also be used when using external_sync.
2021-07-13 15:49:42 +03:00
AndreiGrozav c235e5e583 axi_pwm_gen: Initial commit
axi_pwm_gen is based on util_pulse_gen, it introduces the option of
phase option between pulses(PWMs) and external synchronization.
Documentation available at
https://wiki.analog.com/resources/fpga/docs/axi_pwm_gen
2021-05-07 19:09:32 +03:00