Data to DMA/system memory must be presented in widths of multiple of 8 bits,
however this padding is not optimal if is done in the transport layer
since this will affect the DAC/ADC FIFO or offload storage.
This utility block adds or removes padding from sample stream in case the
sample with is not multiple of 8 bits, and can be placed between the DMA
and FIFO/Offload blocks.
On large projects with multiple channels the databus on the FIFO/AXI
stream interface can get wider that 1024 bits.
This commit allows a wider range for all the interfaces,
in case for the memory mapped interfaces where the range is 32-1024 the
user selects a bus width out of range that will be handled by the IPI.
The 4 parameters are added to facilitate transmiting project
related information to the software. They act as read-only
memory which is written in Vivado when the project builds.
Set 31 to SDI FIFO's almost full threshold
In case of multiple SDI (MISO) lanes, the samples arrives in a parallel
fashion. For example in case of 4 MISO line, at the first latching clock
edge 4 bits of a sample will be saved, one bit into each shift register.
The data reorder module reconstruct the incoming samples from the AXI
stream of the offload module.
Some IPs like JESD link layer were marked as not supported on Versal devices by
the current flow while other not (e.g. TPL).
The auto family support seems to workaround this issue.
This commit fixes an issue in situations where we provide an oversized
transaction to the data offload in TX mode. Previously, the data offload
would stop accepting new data (wr_ready <= 0) after filling up the
internal storage, and get stuck waiting for the input transaction to
end, thus locking up the device.
This commit addresses that issue by allowing the data offload to consume
the full input transaction, even if the tail of the buffer will be
truncated in the output.
Signed-off-by: David Winter <david.winter@analog.com>
This commit adds a new synthesis option to the design, that controls
whether an internal clock domain crossing will be generated. Disabling
this option allows you to use a synchronization signal that is
synchronized to the write clock domain externally, and possibly shared
between multiple devices.
The default value retains the old behavior.
Signed-off-by: David Winter <david.winter@analog.com>
Laszlo Nagy
Nicola Corna
Dan Hotoleanu
stefan.raus
Filip Gherman
David Winter
sergiu arpadi
LIacob106
Istvan Csomortani
Laszlo Nagy
Mihaita Nagy
AndreiGrozav
Adrian Costina
Robin Getz